Memory system with dynamically allocatable non-volatile storage capability

• US 5,680,570 A
• Filed: 09/30/1994
• Issued: 10/21/1997
• Est. Priority Date: 06/12/1991
• Status: Expired due to Term

• Current Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Original Assignee: Quantum Corporation (Chi Ko Investment Co., Ltd.)
• Inventors: Cassidy, Charles F., Rantala, Joseph F., Grooms, John K.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US08/316,057
• Time in Patent Office: 1,117 Days
• Field of Search: 395/440, 395/489, 395/431, 395/432, 395/471, 395/472, 395/483, 395/465, 395/466, 395/182.04
• US Class Current: 711/113
• CPC Class Codes: G06F 11/0796 Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
• CPC Class Codes: G11C 29/74 using duplex memories, i.e. using dual copies

Abstract

A memory system having volatile storage of data destined for secondary storage and smaller intermediate non-volatile storage of some of the data. The volatile memory is an array of DRAM storage devices integrated with the non-volatile memory array of SRAM devices by a mapping logic unit. The DRAM array stores all the data blocks destined for secondary storage. In contrast, the smaller SRAM array stores only the data requiring safe storage, which typically is a subset of the data stored in the DRAM array. The mapping logic unit manages the use of the SRAM array.

Claims

1. A memory system connected between a host central processing unit and a mass storage device having non-volatile secondary storage media, the memory system configured to provide intermediate non-volatile storage to protect data blocks destined for storage on the secondary storage media against loss from a system power failure, said memory system comprising:

a first subsystem of storage elements providing volatile storage of data blocks including the data blocks destined for storage on said secondary storage media;

a second subsystem of storage elements providing non-volatile storage of data blocks stored in said first subsystem which have not yet been stored on the secondary storage media, the block storage capacity of said second subsystem being substantially less than the block storage capacity of said first subsystem; and

a hardware mapping logic unit responsive to block shadow mapping commands from the central processing unit and coupled between said first and second subsystems for mapping block storage address locations of said first subsystem for said data blocks which have not yet been stored on the secondary storage media to block storage address locations of the second subsystem to enable the second subsystem automatically to shadow and store said blocks as said blocks are written by said host central processing unit to the mapped block storage locations of said first subsystem without requiring a separate write operation of said host central processing unit to said second subsystem.

2. The memory system of claim 1 wherein said first and second subsystems are apportioned into pages configured to store said data blocks.

3. The memory system of claim 1 wherein said mapping logic unit comprises shadow block maintaining means for maintaining a list of second subsystem block storage locations available to shadow corresponding first subsystem block storage locations.

4. The memory system of claim 3 wherein said shadow block maintaining means includes a page stack capable of storing a plurality of page stack entries.

5. The memory system of claim 4 wherein said page stack comprises a plurality of data fields and address fields referenced by a pointer.

6. The memory system of claim 5 wherein each of said data fields contains a page stack entry identifying a block storage location address in said second subsystem.

7. The memory system of claim 6 wherein each of said address fields contains an address for each page stack entry in said page stack.

8. The memory system of claim 7 wherein said pointer contains an address of a page stack entry identifying said particular one of said block locations of said second subsystem available to shadow a corresponding block location of said first subsystem.

9. The memory system of claim 3 wherein said mapping logic unit comprises means for linking said block storage locations of said second subsystem to said block storage locations of said first subsystem.

10. The memory system of claim 9 wherein said linking means includes a page stack and a tag storage array, the page stack for allocating available shadow block storage locations of said second subsystem, and said tag storage array for linking said block storage locations of said first subsystem to said available shadow block storage locations of said second subsystem.

11. The memory system of claim 10 wherein said tag storage array comprises non-volatile storage for a plurality of data fields and address fields.

12. The memory system of claim 11 wherein each of said data fields contains a tag entry stored in said page stack for linking a block storage location address of said first subsystem with an available shadow block storage location address of said second subsystem.

13. The memory system of claim 12 wherein each of said data fields further contains allocation determining means for determining if a particular one of said shadow block storage locations of said second subsystem has been allocated to shadow a corresponding block storage location of said first subsystem.

14. The memory system of claim 13 wherein said allocation determining means comprises means for writing and reading an allocate bit in a said data field.

15. The memory system of claim 14 wherein each of said data fields further contains valid data determining means for determining if said particular one of said shadow block storage locations of said second subsystem contains valid data not yet written to said secondary storage media.

16. The memory system of claim 15 wherein said valid data determining means comprises means for writing and reading a valid bit in a said data field.

17. The memory system of claim 16 wherein said address field of said tag storage array contains an address that identifies one of said plurality of tag entries, said address corresponding to one of said data blocks in said first subsystem.

18. The memory system of claim 1 wherein said secondary storage media comprises a magnetic mass storage device within a classification of hard disk drives and tape drives.

19. The memory system of claim 1 wherein the hardware mapping logic unit includes shadow block reallocation means responsive to shadow mapping deallocation commands from said central processing unit for releasing shadow block storage locations of said second subsystem containing said data blocks determined to be written to said non-volatile secondary storage media.

20. The memory system of claim 1 wherein the first memory subsystem comprises a dynamic random access memory array, and wherein the second memory subsystem comprises a battery backed-up static random access memory array.

21. A memory system of a computer including a central processing unit and a mass storage device providing non-volatile secondary storage media, the memory system configured to provide intermediate non-volatile storage of data destined for the secondary storage media during a computer power loss, said memory system comprising:

a dynamic random access memory (DRAM) array of storage elements apportioned into DRAM pages configured to provide volatile storage of data destined for said secondary storage media;

a static random access memory (SRAM) array of storage elements apportioned into SRAM pages configured to provide non-volatile storage of data corresponding to selected data stored in said DRAM array, the storage capacity of said SRAM array being substantially less than the storage capacity of said DRAM array;

a hardware mapping logic unit responsive to page shadow mapping commands from the central processing unit and coupled between said DRAM array and said SRAM array for mapping page storage locations of said DRAM array for said data pages which have not yet been stored on the secondary storage media to page storage locations of the SRAM array to enable the SRAM array automatically to shadow and store said pages simultaneously as said pages are written by said host central processing unit to the mapped page storage locations of said DRAM array without requiring a separate write operation of said host central processing unit to the SRAM array, said hardware mapping logic unit including;

allocation determining means for determining if a particular one of said SRAM pages has been allocated to shadow a corresponding DRAM page; and

valid data determining means for determining if said particular one of said SRAM pages contains valid data;

whereby after the power loss, said data stored in said particular one of said SRAM pages is retrieved in response to said particular one of said SRAM pages having been allocated and said particular one of said SRAM pages having valid data.

22. The memory system of claim 21 wherein said hardware mapping logic unit comprises:

a page stack for maintaining a list of SRAM pages available to shadow corresponding DRAM pages; and

a tag array for linking said SRAM pages to said DRAM pages, said tag array including a plurality of data fields.

23. The memory system of claim 21 wherein said hardware mapping logic unit comprises an allocate bit located in each of said data fields of said tag array;

and said valid data determining means comprises a valid bit located in each of said data fields of said tag array.

24. A method for protecting data pages against loss in a computing system which have been modified by a central processing unit before being written onto non-volatile media of a mass storage device connected to the central processing unit, the method comprising the steps of:

providing a dynamic random access memory (DRAM) array of storage elements apportioned into DRAM pages configured for volatile storage of data pages including the data pages destined for said secondary storage media;

providing a battery-backed-up static random access memory (SRAM) array of storage elements apportioned into SRAM pages configured to provide non-volatile storage of the data pages stored in said DRAM array destined for said secondary storage media, the page storage capacity of said SRAM array being substantially less than the page storage capacity of said DRAM array;

mapping with a mapping logic unit responsive to page shadow mapping commands from the central processing unit page storage locations of said DRAM array for said data pages which are destined for said secondary storage media to available page storage locations of the SRAM array, and

writing in a single writing step said data pages to page storage locations of said DRAM array and thereby automatically writing said data pages to shadow data page storage locations of said SRAM array mapped to the same page storage locations of said DRAM array by said mapping step.