Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers

• US 5,680,572 A
• Filed: 07/15/1996
• Issued: 10/21/1997
• Est. Priority Date: 02/28/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Akkary, Haitham, Glew, Andrew F., Hinton, Glenn J., Joshi, Mandar S., Lince, Brent E., Konigsfeld, Kris G., Madland, Paul D., Abramson, Jeffrey M.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Ellis, Kevin L.
• Application Number:
  US08/680,109
• Time in Patent Office: 463 Days
• Field of Search: 395/445, 395/460, 395/465, 395/468, 395/473, 395/458, 395/481, 395/453
• US Class Current: 711/126
• CPC Class Codes: G06F 12/0859 with reload from main memory

Abstract

A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.

Claims

1. A cache memory system comprising:

(a) a data array for storing a first plurality of lines of data;

(b) a tag array for storing a first plurality of line addresses corresponding to the first plurality of lines of data stored in the data array;

(c) a multi-purpose buffer assembly, including control logic, a plurality of input and output ports, a plurality of identical multi-purpose line buffers, and a plurality of address matching circuitry, correspondingly coupled to each other, and coupled to the data and tag arrays, for staging a second plurality of lines of data and corresponding line addresses, in response to a plurality of predetermined operating events, including cache misses of load and store operations targeting cacheable data, and sequences of successive store operations with each sequence targeting the same line of cacheable or non-cacheable data, and for independently responding by each line buffer to load and store operations targeting the buffered lines of data.

2. The cache memory system as set forth in claim 1, wherein each line buffer, when allocated to buffer a line of data and the corresponding line address, in response to a cache miss of a load/store operation targeting cacheable data, outputs the buffered data and corresponding line address for the data and tag arrays after receiving the entire line of data.

3. The cache memory system as set forth in claim 1, wherein each line buffer, when allocated to buffer a line of data and the corresponding line address, in response to a sequence of successive store operations targeting the same line of cacheable or non-cacheable data, outputs the buffered data and the corresponding line address for either the data and tag arrays or an external system memory, depending on whether the buffered data are cacheable or not, said output being performed when all data positions of the allocated line buffer have been written into or when the sequence of successive store operations targeting the same line terminates.

4. The cache memory system as set forth in claim 1, wherein each line buffer, regardless of whether the line buffer is allocated to buffer a line of data and the corresponding line address, in response to a cache miss of a load/store operation targeting cacheable data or to a sequence of successive store operations targeting the same line of cacheable or non-cacheable data, outputs requested ones of the buffered data in response to a load operation targeting the buffered line.

5. The cache memory system as set forth in claim 1, wherein each line buffer, regardless of whether the line buffer is allocated to buffer a line of data and the corresponding line address in response to a cache miss of a load/store operation targeting cacheable data or to a sequence of successive store operations targeting the same line of cacheable or non-cacheable data, stores store data of a store operation targeting the buffered line into the line buffer.

6. The cache memory system as set forth in claim 1, wherein the predetermined events further include split load operations, spawned from load operations targeting misaligned cacheable or non-cacheable data, to load aligned subsets of the misaligned cacheable or non-cacheable data.

7. The cache memory system as set forth in claim 6, wherein each line buffer, when allocated to buffer a line of data and the corresponding line address, in response to a split load operation spawned to load an aligned subset of misaligned cacheable or non-cacheable data, outputs the buffered data for combination with the other aligned subset(s) to constitute the targeted misaligned data, in coordination with the data array and/or other line buffer(s).

8. The cache memory system as set forth in claim 6, wherein each line buffer, regardless of whether the line buffer is allocated to buffer a line of data and the corresponding line address, in response to a cache miss of a load/store operation targeting cacheable data, or to a sequence of successive store operations targeting the same line of cacheable or non-cacheable data, or to a split load operation targeting an aligned subset of misaligned cacheable or non-cacheable data, outputs requested ones of the buffered data in response to a load operation targeting the buffered line.

9. The cache memory system as set forth in claim 6, wherein each line buffer, regardless of whether the line buffer is allocated to buffer a line of data and the corresponding line address, operation targeting cache miss of a load/store operation targeting cacheable data, or to a sequence of successive store operations targeting the same line of cacheable or non-cacheable data, or to a split load operation targeting an aligned subset of misaligned cacheable or non-cacheable data, stores store data of a store operation targeting the buffered line into the line buffer.

10. A cache memory system comprising:

(a) a data array for storing a first plurality of lines of data;

(b) a tag array for storing a first plurality of line addresses corresponding to the first plurality of lines of data stored in the data array;

(c) a multi-purpose buffer assembly, including control logic, a plurality of input and output ports, a plurality of identical multi-purpose line buffers, and a plurality of address matching circuitry, correspondingly coupled to each other, and coupled to the data and tag arrays, for staging a second plurality of lines of data and corresponding line addresses, in response to a plurality of predetermined operating events, including cache misses of load and store operations targeting cacheable data, and split load operations spawned to load aligned subsets of misaligned cacheable or non-cacheable data targeted by misaligned load operations, and for independently responding by each line buffer to load and store operations targeting the buffered lines of data.

11. The cache memory system as set forth in claim 10, wherein each line buffer, when allocated to buffer a line of data and the corresponding line address, in response to a cache miss of a load/store operation targeting cacheable data, outputs the buffered data and corresponding line address for the data and tag arrays after receiving the entire line of data.

12. The cache memory system as set forth in claim 10, wherein each line buffer, when allocated to buffer a line of data and the corresponding line address, in response to a split load operation targeting an aligned subset of misaligned cacheable or non-cacheable data, outputs the buffered data for combination with the other aligned subset(s) to constitute the targeted misaligned data, in coordination with the data array and/or other line buffer(s).

13. The cache memory system as set forth in claim 10, wherein each line buffer, regardless of whether the line buffer is allocated to buffer a line of data and the corresponding line address, in response to a cache miss of a load/store operation targeting cacheable data, or to a split load operation targeting an aligned subset of misaligned cacheable or non-cacheable data, outputs requested ones of the buffered data in response to a load operation targeting the buffered line.

14. The cache memory system as set forth in claim 10, wherein each line buffer, regardless of whether the line buffer is allocated to buffer a line of data and the corresponding line address, in response to a cache miss of a load/store operation targeting cacheable data, or to a split load operation targeting an aligned subset of misaligned cacheable or non-cacheable data, stores store data of a store operation targeting the buffered line into the line buffer.

15. A method for operating a cache memory system, the method comprising the steps of:

(a) storing a first plurality of lines of data in a data array;

(b) storing a first plurality of line addresses corresponding to the first plurality of lines of data stored in the data array in a tag array;

(c) staging a second plurality of lines of data and corresponding line addresses, in response to a plurality of predetermined operating events, including cache misses, and sequences of successive store operations, in a multi-purpose buffer assembly, each cache miss being triggered by a load or a store operation targeting cacheable data, and each sequence of successive store operations targeting the same line of cacheable or non-cacheable data, and the multi-purpose buffer assembly having control logic, a plurality of input and output ports, a plurality of identical multi-purpose purpose line buffers, and a plurality of address matching circuitry, correspondingly coupled to each other, and coupled to the data and tag arrays; and

(d) independently responding by each line buffer to load and store operations targeting the buffered lines of data by the multi-purpose buffer assembly.

16. The method as set forth in claim 15, wherein the method further includes step (e) outputting the buffered data and corresponding line address for the data and tag arrays by each line buffer allocated to buffer a line in response to a cache miss of a load/store operation targeting cacheable data, when the line buffer receives the entire line of data.

17. The method as set forth in claim 15, wherein the method further includes step (e) outputting the buffered data and the corresponding line address for either the data and tag arrays or an external system memory, depending on whether the buffered data are cacheable or not, by each line buffer allocated to buffer a line in response to a sequence of successive store operations targeting the same line of cacheable or non-cacheable data, said outputting being performed when all data positions of the allocated line buffer have been written into or when the sequence of successive store operations targeting the same line terminates.

18. The method as set forth in claim 15, wherein step (d) comprises outputting requested ones of the buffered data in response to a load operation targeting the buffered line by each line buffer, regardless of whether the line buffer is allocated to buffer a line of data and the corresponding line address in response to a cache miss of a load/store operation targeting cacheable data or to a sequence of successive store operations targeting the same line of cacheable or non-cacheable data.

19. The method as set forth in claim 15, wherein step (d) comprises storing store data of a store operation targeting a buffered line into the buffering line buffer, regardless of whether the buffering line buffer is allocated to buffer a line of data and the corresponding line address in response to a cache miss of a load/store operation targeting cacheable data, or to a sequence of successive store operations targeting the same line of cacheable or non-cacheable data.

20. The method as set forth in claim 15, wherein the predetermined events of step (d) further include split load operations spawned from load operations targeting misaligned data to load aligned subsets of the misaligned cacheable or non-cacheable data.

21. The method as set forth in claim 20, the method further comprises step (e) outputting the buffered data for combination with the other aligned subset(s) to constitute the targeted misaligned data, in coordination with the data array and/or other line buffer(s), by each line buffer allocated to buffer a line of data and the corresponding line address, in response to a split load operation targeting an aligned subset of misaligned cacheable or non-cacheable data.

22. The method as set forth in claim 20, wherein step (d) comprises outputting requested ones of the buffered data in response to a load operation targeting the buffered line by each line buffer, regardless of whether the line buffer is allocated to buffer a line of data and the corresponding line address in response to a cache miss of a load/store operation targeting cacheable data, or to a sequence of successive store operations targeting the same line of cacheable or non-cacheable data, or to a split load operation targeting an aligned subset of misaligned cacheable or non-cacheable data.

23. The method as set forth in claim 20, wherein step (d) comprises storing store data of a store operation targeting a buffered line into the buffering line buffer, regardless of whether the buffering line buffer is allocated to buffer a line of data and the corresponding line address in response to a cache miss of a load/store operation targeting cacheable data, or to a sequence of successive store operations targeting the same line of cacheable or non-cacheable data, or to a split load operation targeting an aligned subset of misaligned cacheable or non-cacheable data.

24. A method for operating a cache memory system, the method comprising the steps of:

(a) storing a first plurality of lines of data in a data array;

(b) storing a first plurality of line addresses corresponding to the first plurality of lines of data stored in the data array in a tag array;

(c) staging a second plurality of lines of data and corresponding line addresses, in response to a plurality of predetermined operating events, including cache misses and split load operations, in a multi-purpose buffer assembly, each cache miss being triggered by a load or store operation targeting cacheable data, each split load operation being spawned to load aligned subsets of misaligned cacheable or non-cacheable data targeted by a misaligned load operation, the multi-buffer assembly including a plurality of input and output ports, a plurality of identical multi-purpose, line buffers, and a plurality of address matching circuitry, correspondingly coupled to each other and to the data and tag arrays; and

(d) independently responding by each line buffer to load and store operations targeting the buffered lines of data.

25. The method as set forth in claim 24, wherein the method further comprises step (e) outputting the buffered data and corresponding line address for the data and tag arrays by each line buffer allocated to buffer a line of data and the corresponding line address, in response to a cache miss by a load or store operation targeting cacheable data, the outputting being performed after the line buffer has received the entire line of data each line buffer.

26. The method as set forth in claim 24, wherein the method further comprises step (e) outputting the buffered data for combination with the other aligned subset(s) to constitute the targeted misaligned data, in coordination with the data array and/or other line buffer(s) by each line buffer allocated to buffer a line of data and the corresponding line address, in response to a split load operation targeting an aligned subset of misaligned cacheable or non-cacheable data.

27. The method as set forth in claim 24, wherein step (d) comprises outputting requested ones of the buffered data in response to a load operation targeting the buffered line by each line buffer, regardless of whether the line buffer is allocated to buffer a line of data and the corresponding line address in response to a cache miss of a load or store operation targeting cacheable data, or to a split load operation targeting an aligned subset of misaligned cacheable or non-cacheable data.

28. The method as set forth in claim 24, wherein step (d) comprises storing store data of a store operation targeting a buffered line into the buffering line buffer, regardless of whether the buffering line buffer is allocated to buffer a line of data and the corresponding line address in response to a cache miss of a load or store operation targeting cacheable data, or to a split load operation targeting an aligned subset of misaligned cacheable or non-cacheable data.