Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers
First Claim
1. A cache memory system comprising:
- (a) a data array for storing a first plurality of lines of data;
(b) a tag array for storing a first plurality of line addresses corresponding to the first plurality of lines of data stored in the data array;
(c) a multi-purpose buffer assembly, including control logic, a plurality of input and output ports, a plurality of identical multi-purpose line buffers, and a plurality of address matching circuitry, correspondingly coupled to each other, and coupled to the data and tag arrays, for staging a second plurality of lines of data and corresponding line addresses, in response to a plurality of predetermined operating events, including cache misses of load and store operations targeting cacheable data, and sequences of successive store operations with each sequence targeting the same line of cacheable or non-cacheable data, and for independently responding by each line buffer to load and store operations targeting the buffered lines of data.
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Accused Products
Abstract
A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.
56 Citations
28 Claims
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1. A cache memory system comprising:
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(a) a data array for storing a first plurality of lines of data; (b) a tag array for storing a first plurality of line addresses corresponding to the first plurality of lines of data stored in the data array; (c) a multi-purpose buffer assembly, including control logic, a plurality of input and output ports, a plurality of identical multi-purpose line buffers, and a plurality of address matching circuitry, correspondingly coupled to each other, and coupled to the data and tag arrays, for staging a second plurality of lines of data and corresponding line addresses, in response to a plurality of predetermined operating events, including cache misses of load and store operations targeting cacheable data, and sequences of successive store operations with each sequence targeting the same line of cacheable or non-cacheable data, and for independently responding by each line buffer to load and store operations targeting the buffered lines of data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A cache memory system comprising:
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(a) a data array for storing a first plurality of lines of data; (b) a tag array for storing a first plurality of line addresses corresponding to the first plurality of lines of data stored in the data array; (c) a multi-purpose buffer assembly, including control logic, a plurality of input and output ports, a plurality of identical multi-purpose line buffers, and a plurality of address matching circuitry, correspondingly coupled to each other, and coupled to the data and tag arrays, for staging a second plurality of lines of data and corresponding line addresses, in response to a plurality of predetermined operating events, including cache misses of load and store operations targeting cacheable data, and split load operations spawned to load aligned subsets of misaligned cacheable or non-cacheable data targeted by misaligned load operations, and for independently responding by each line buffer to load and store operations targeting the buffered lines of data. - View Dependent Claims (11, 12, 13, 14)
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15. A method for operating a cache memory system, the method comprising the steps of:
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(a) storing a first plurality of lines of data in a data array; (b) storing a first plurality of line addresses corresponding to the first plurality of lines of data stored in the data array in a tag array; (c) staging a second plurality of lines of data and corresponding line addresses, in response to a plurality of predetermined operating events, including cache misses, and sequences of successive store operations, in a multi-purpose buffer assembly, each cache miss being triggered by a load or a store operation targeting cacheable data, and each sequence of successive store operations targeting the same line of cacheable or non-cacheable data, and the multi-purpose buffer assembly having control logic, a plurality of input and output ports, a plurality of identical multi-purpose purpose line buffers, and a plurality of address matching circuitry, correspondingly coupled to each other, and coupled to the data and tag arrays; and (d) independently responding by each line buffer to load and store operations targeting the buffered lines of data by the multi-purpose buffer assembly. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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24. A method for operating a cache memory system, the method comprising the steps of:
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(a) storing a first plurality of lines of data in a data array; (b) storing a first plurality of line addresses corresponding to the first plurality of lines of data stored in the data array in a tag array; (c) staging a second plurality of lines of data and corresponding line addresses, in response to a plurality of predetermined operating events, including cache misses and split load operations, in a multi-purpose buffer assembly, each cache miss being triggered by a load or store operation targeting cacheable data, each split load operation being spawned to load aligned subsets of misaligned cacheable or non-cacheable data targeted by a misaligned load operation, the multi-buffer assembly including a plurality of input and output ports, a plurality of identical multi-purpose, line buffers, and a plurality of address matching circuitry, correspondingly coupled to each other and to the data and tag arrays; and (d) independently responding by each line buffer to load and store operations targeting the buffered lines of data. - View Dependent Claims (25, 26, 27, 28)
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Specification