Interconnect failure detection and cache reset apparatus

• US 5,680,575 A
• Filed: 05/17/1995
• Issued: 10/21/1997
• Est. Priority Date: 02/20/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Salyer, Gregory, Fasano, Louis Thomas, Bartow, Neil George, Gregg, Thomas Anthony, Capowski, Robert Stanley, Westcott, Douglas Wayne
• Primary Examiner(s): Treat, William M.
• Assistant Examiner(s): Maung, Zarni
• Application Number:
  US08/443,293
• Time in Patent Office: 888 Days
• Field of Search: 395/468, 395/473, 395/471, 395/575, 395/375, 395/200.14, 395/200.1, 395/200.01
• US Class Current: 711/141
• CPC Class Codes: G06F 13/122 where hardware performs an I/O function other than control of data transfer
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: H04J 3/0629 in a network, e.g. in combination with switching or multiplexing, slip buffers
• CPC Class Codes: H04L 69/14 Multichannel or multilink protocols
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04L 69/40 for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection management of faults, events, alarms or notifications in data switching networks H04L41/06
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A system for resetting a cache in a first device connected by a multilinelink to a memory in a second device. A transceiver in the first element connects to one end of each of the link lines and a transceiver in the second device connects to the other end. The transmitter in the first device transceiver is disabled in response to a failure of the transceiver to receive messages from the second device. The transmitter in the first device transceiver also selectively sends a reset sequence to the receiver in the second device. A detector detects when all of the receivers in the second device have either received a reset sequence or have detected that a transmitter in the first device is disabled. The detector sets a latch in response, representing that data in the second device cache is invalid. Optionally, the second device has responders which send responses over the link lines indicating receipt of a reset sequence. The transmitters in the first device switch to a disabled state when the responses are not received within a specified period.

Claims

1. In a data processing complex with interconnected elements, an apparatus for maintaining cache integrity between two elements of said complex comprising:

a first element having a data storage means;

a second element having a cache data storage means;

a channel for connecting said first and second elements, comprising

a channel apparatus associated with said first element including

means for generating a cache reset sequence,

means for generating a plurality of transmitter disable signals, and

a plurality of transmitters, each having means for switching to a disabled state in response to a corresponding one of said transmitter disable signals, and at least one of said transmitters having means for outputting said cache reset sequence concurrent with an absence of a corresponding one of said transmitter disable signals;

a plurality of transmission lines, each having one end connected to a corresponding one of said transmitters;

a channel apparatus associated with said second element including

a plurality of receiving means connected to another end of a corresponding one of said transmission lines, each of said receiving means having means for detecting said transmitted reset sequence and generating a reset detect signal in response and each having means for detecting that the corresponding transmitter at the other end of said transmitting line is in said disabled state and generating a line failure signal in response, and

means for generating a plurality of latch enable signals, each of said latch enable signals corresponding to an associated one of said plurality of receiving means, and each latch enable signal having a first value representing at least one of said reset detect signal and said line failure signal being generated by said associated one of said receiving means;

means for generating a cache reset latch signal based on said plurality of latch enable signals; and

a cache reset latch which sets based on said cache reset latch signal, said cache reset latch indicating that said channel has been in a reset state and that a data in said second element cache data storage means is not valid.

2. An apparatus according to claim 1 wherein:

the latch is set when it has been detected that the transceivers have been reset on all receivers of the operational link; and

said cache reset latch signal is generated based on a concurrence of all of said plurality of latch enable signals whereby the cache reset latch is set when all of said receiving means have detected either the reset sequence or that the corresponding transmitter has been disabled, or any combination so long as every receiver detects one of these two conditions.

3. An apparatus according to claim 1 further comprising

means associated with said second element for generating and outputting onto said transmission line a response sequence in response to receiving said reset sequence;

and

wherein said means for switching the transmitter to said disabled state switches the transmitter to said disabled state if the response sequence is not received in a specified time period relative to said transmitter outputting said reset sequence.

4. An apparatus according to claim 3 wherein:

the specified time period is 20 milliseconds.

5. An apparatus according to claim 3 wherein:

a reset state is complete upon all of the transmitters being one of disabled and having received the response sequence.

6. An apparatus according to claim 3

further comprising a means associated with said second device for detecting an absence of a carrier signal in said transmission line, and wherein

a reset is complete after the transmitter has been in the disabled state for a period of time sufficient for the absence of carrier to be detected.

7. An apparatus according to claim 6 wherein:

the period of time for a loss of carrier to be detected is 110 milliseconds.

8. An apparatus according to claim 6 wherein:

the carrier is an optical signal.