Redundant array of solid state memory devices

• US 5,680,579 A
• Filed: 01/25/1996
• Issued: 10/21/1997
• Est. Priority Date: 11/10/1994
• Status: Expired due to Fees

• Current Assignee: Kaman Aerospace Corporation (Kaman Corporation)
• Original Assignee: Kaman Aerospace Corporation (Kaman Corporation)
• Inventors: So, Yin Cheung, Shumski, Gregory J., Solari, Peter L., Young, Paul R.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/540,338
• Time in Patent Office: 635 Days
• Field of Search: 365/200, 365/201, 395/484, 395/497.01, 395/497.04, 395/427, 371/40.4, 371/49.1, 371/51.1, 371/50.1
• US Class Current: 711/157
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system

Abstract

A device employing a redundant array of solid state memory devices is presented, whereby RAID technology architecture is uniquely combined with solid state memory devices. The devices comprises a plurality of circuit boards assemblies mounted within a housing, preferably a housing which fits into a standard 51/4 inch computer drive bay or a rack mount housing. The circuit board assemblies are electrically connected to solid state memory devices, for example, flash memory PCMCIA cards. A data path controller circuit provides the interface between a host system and the flash memory cards.

Claims

1. A method for storage of data and interfacing with a host system, comprising the steps of:

configuring a plurality of solid state memory devices, said plurality of solid state memory devices comprises a plurality of flash memory devices, each of said flash memory devices is packaged in a PCMCIA format; and

presenting said plurality of solid state memory devices to the host system as a single logical solid state memory device.

2. The method claim 1 wherein said step of presenting comprises:

controlling a data path between said solid state memory devices and the host system;

generating parity at said solid state memory devices; and

stripping data across said solid state memory devices.

3. The method of claim 2 further comprising the steps of:

redundantly storing executable operating routines on said solid state memory devices;

storing boot-up routines at a first memory means for system boot-up;

executing said boot-up routines;

downloading said operating routines from said solid state memory devices to second memory means in response to execution of said boot-up routines;

executing said operating routines in response to execution of said boot-up routines; and

managing system setup in response to execution of said operating routines.

4. The method of claim 1 wherein said step of configuring comprises configuring said solid state memory devices to be read independently.

5. The method of claim 1 wherein said step of configuring comprises configuring said solid state memory devices so that identical data is written onto at least two of said solid state memory devices.

6. The method of claim 1 wherein said step of configuring comprises configuring said solid state memory devices to utilize complex error correction codes on at least two of said solid state memory devices.

7. The method of claim 1 wherein said step of configuring comprises configuring said solid state memory devices to employ bit-interleaved parity wherein one of said solid state memory devices supports parity which is shared among said solid state memory devices with parallel access.

8. The method of claim 1 wherein said step of configuring comprises configuring said solid state memory devices to employ block-interleaved parity wherein one of said solid state memory devices supports parity which is shared among said solid state memory devices with block stripping.

9. The method of claim 1 wherein said step of configuring comprises configuring said solid state memory devices so that parity is supported across all of said solid state memory devices with independent access.

10. A method for storage of data and interfacing with a host system, comprising the steps of:

configuring a plurality of solid state memory devices; and

presenting said plurality of solid state memory devices to the host system as a single logical solid state memory device, said step of presenting comprising,

(1) controlling a data path between said solid state memory devices and the host system,

(2) generating parity at said solid state memory devices, and

(3) stripping data across said solid state memory devices.

11. The method of claim 10 wherein said plurality of solid state memory devices comprise a plurality of flash memory devices.

12. The method of claim 10 further comprising the steps of:

redundantly storing executable operating routines on said solid state memory devices;

storing boot-up routines at a first memory means for system boot-up;

executing said boot-up routines;

downloading said operating routines from said solid state memory devices to second memory means in response to execution of said boot-up routines;

executing said operating routines in response to execution of said boot-up routines; and

managing system setup in response to execution of said operating routines.

13. The method of claim 10 wherein said step of configuring comprises configuring said solid state memory devices to be read independently.

14. The method of claim 10 wherein said step of configuring comprises configuring said solid state memory devices so that identical data is written onto at least two of said solid state memory devices.

15. The method of claim 10 wherein said step of configuring comprises configuring said solid state memory devices to utilize complex error correction codes on at least two of said solid state memory devices.

16. The method of claim 10 wherein said step of configuring comprises configuring said solid state memory devices to employ bit-interleaved parity wherein one of said solid state memory devices supports parity which is shared among said solid state memory devices with parallel access.

17. The method of claim 10 wherein said step of configuring comprises configuring said solid state memory devices to employ block-interleaved parity wherein one of said solid state memory devices supports parity which is shared among said solid state memory devices with block stripping.

18. The method of claim 10 wherein said step of configuring comprises configuring said solid state memory devices so that parity is supported across all of said solid state memory devices with independent access.

19. A method for storage of data and interfacing with a host system, comprising the steps of:

configuring a plurality of solid state memory devices so that identical data is written onto at least two of said solid state memory devices; and

presenting said plurality of solid state memory devices to the host system as a single logical solid state memory device.

20. The method of claim 19 wherein said plurality of solid state memory devices comprise a plurality of flash memory devices.

21. A method for storage of data and interfacing with a host system, comprising the steps of:

configuring a plurality of solid state memory devices to utilize complex error correction codes on at least two of said solid state memory devices; and

presenting said plurality of solid state memory devices to the host system as a single logical solid state memory device.

22. The method of claim 21 wherein said plurality of solid state memory devices comprise a plurality of flash memory devices.

23. A method for storage of data and interfacing with a host system, comprising the steps of:

configuring a plurality of solid state memory devices to employ bit-interleaved parity wherein one of said solid state memory devices supports parity which is shared among said solid state memory devices with parallel access; and

presenting said plurality of solid state memory devices to the host system as a single logical solid state memory device.

24. The method of claim 23 wherein said plurality of solid state memory devices comprise a plurality of flash memory devices.

25. A method for storage of data and interfacing with a host system, comprising the steps of:

configuring a plurality of solid state memory devices to employ block-interleaved parity wherein one of said solid state memory devices supports parity which is shared among said solid state memory devices with block stripping; and

presenting said plurality of solid state memory devices to the host system as a single logical solid state memory device.

26. The method of claim 25 wherein said plurality of solid state memory devices comprise a plurality of flash memory devices.

27. A method for storage of data and interfacing with a host system, comprising the steps of:

configuring a plurality of solid state memory devices so that parity is supported across all of said solid state memory devices with independent access; and

presenting said plurality of solid state memory devices to the host system as a single logical solid state memory device.

28. The method of claim 27 wherein said plurality of solid state memory devices comprise a plurality of flash memory devices.