Data processor having precise timer output

• US 5,680,593 A
• Filed: 08/03/1995
• Issued: 10/21/1997
• Est. Priority Date: 08/03/1994
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Hiiragizawa, Yasunori
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/510,651
• Time in Patent Office: 810 Days
• Field of Search: 395/550, 395/555
• US Class Current: 713/500
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock

Abstract

A data processor is disclosed which shows an improved real time performance by carrying out the starting and clearing operations of a timer in response to an external trigger input. In the timer unit of the unit of the data processor, a flip-flop is set during the low level period of a count enable signal, and a prescaler and a timer are cleared and inactivated by bringing the outputs of OR gates to the-high level. As the count-enable signal goes to the high level, an edge-detection circuit output a detection pulse by detecting a level change of the external trigger signal. The flip-flop is reset by the detection pulse, and the operation of the prescaler is started and a count clock is supplied to the timer to start the counting operation of the timer.

Claims

1. A data processor comprising first means for, when activated, producing a pulse signal in response to a clock signal, storage means for temporarily storing control information settable to one of first and second states, said control information being generated by a microprocessor responsive to a level change in a trigger signal, second means responsive to said first state of said control information for deactivating said first means, third means for detecting supply of said trigger signal to produce a detection signal, and fourth means responsive to said second state of said control information and said detection signal for activating said first means, wherein said fourth means establishes a constant time interval between a level change in said trigger signal and output of said pulse signal.

2. The data processor as claimed in claim 1, wherein said first means includes a timer receiving and counting said clock signal and said fourth means allows said timer to receive and count said clock signal.

3. The data processor as claimed in claim 2, wherein said third means produces said detection signal when said trigger signal is changed in level.

4. A data processor comprising, a counter enable register whose data is set by a central processing unit, an edge detection circuit which detects a change of a level of a trigger signal input and outputs a detection signal, control means receiving input from said counter enable register and said edge detection circuit, said control means outputting a signal with an inactive level when said set data has a first value and for outputting a signal with an active level during the period until said set data reaches said first value when said set data has a second value and said trigger signal goes to the active level, a prescaler which is inactivated when the output of said control means is at the inactive level and outputs a modified clock signal obtained by scaling an input reference clock when the output of said control means is at the active level, and a timer which is inactivated when said set data is at the first value and is activated when said set data is at the second value and counts the scaled clock output by said prescaler, wherein said control means establishes a constant time interval between a level change in said trigger signal and activation of said timer.

5. The data processor as claimed in claim 4, wherein said control means further includes means which brings the output to the inactive level in response to an overflow signal output when said timer has attained a specified counted number.

6. The data processor as claimed in claim 4, further comprising a first and a second comparison means receiving and comparing the output of said timer with respective stored first and second data and outputting first and second comparison results, and generation means for generating a pulse in response to the comparison results of said first comparison means and said second comparison means.

7. The data processor as claimed in claim 6, wherein said generation means is an RS flip-flop having a set terminal receiving the first comparison result and a reset terminal receiving the second comparison result.