Input-output (I/O) structure with capacitively triggered thyristor for electrostatic discharge (ESD) protection

• US 5,682,047 A
• Filed: 06/07/1995
• Issued: 10/28/1997
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Ku, Yen-Hui, Consiglio, Rosario
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Abraham, Fetsum
• Application Number:
  US08/484,003
• Time in Patent Office: 874 Days
• Field of Search: 257/173, 257/172, 257/107, 257/355, 257/357, 257/358, 257/360, 327/432, 327/453, 327/438, 327/439, 327/440, 327/465, 327/470
• US Class Current: 257/335
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices

Abstract

An input/output structure includes a microelectronic device connected in circuit between a contact pad and a reference potential, and a thyristor device for protecting the microelectronic device from electrostatic discharge. The thyristor device includes first and second terminals connected to the contact pad and to the reference potential respectively, a PNPN thyristor structure including a first P-region, a first N-region, a second P-region and a second N-region disposed in series between the first and second terminals, and an electrode for inducing an electric field into the second P-region. The induced electric field increases the number of charge carriers in the second P-region, and enables the device to be triggered at a lower voltage applied between the first and second terminals. The electrode includes an insulated gate, and can be connected to either the first or second terminal. The gate can include a thick field oxide layer, or a thin oxide layer to further reduce the triggering voltage. A differentiator including a capacitor connected between the first terminal and the electrode and a resistor connected between the second terminal and the electrode prevents false triggering during normal operation. A metal interconnection layer includes an anode section which is connected to the N-region and to the second terminal, and a cathode section which is connected to the P-region, the first terminal and the electrode, such that the cathode section laterally surrounds the anode section.

Claims

1. An input/output structure comprising:

microelectronic device connected in circuit between a contact pad and a reference potential;

a thyristor device for protecting the microelectronic device from electrostatic discharge, the thyristor device including;

a first terminal connected to the contact pad;

a second terminal connected to the reference potential;

a PNPN thyristor structure including a first P-region, a first N-region, a second P-region and a second N-region disposed in series between the first and second terminals; and

an electrode for inducing an electric field into one of the first N-region and the second P-region;

a capacitor connected between the first terminal and the electrode; and

a resistor connected between the second terminal and the electrode.

2. An input/output structure as in claim 1, in which:

the first terminal is connected in circuit to the first N-region; and

the second terminal is connected in circuit to the second P-region.

3. An input/output structure as in claim 1, further comprising:

a first resistor connected between the first terminal and the first N-region; and

a second resistor connected between the second terminal and the second P-region.

4. An input/output structure as in claim 1, in which the electrode comprises an insulated gate.

5. An input/output structure as in claim 4, in which the insulated gate comprises:

a field oxide layer; and

an electrically conductive layer formed on the field oxide layer.

6. An input/output structure as in claim 5, in which the field oxide layer has a thickness of approximately 8,000 Angstroms.

7. An input/output structure as in claim 5, further comprising:

a resistor connected between the microelectronic device and the contact pad, in which;

the first terminal is connected to the contact pad.

8. An input/output structure as in claim 4, in which the insulated gate comprises:

a thin oxide layer; and

an electrically conductive layer formed on the thin oxide layer.

9. An input/output structure as in claim 8, in which the thin oxide layer has a thickness of approximately 80 Angstroms.

10. An input/output structure as in claim 1, in which the electrode is disposed for capacitively inducing an electric field into the first N-region.

11. An input/output structure comprising:

a microelectronic device connected in circuit between a contact pad and a reference potential;

a thyristor device for protecting the microelectronic device from electrostatic discharge, the thyristor device including;

a first terminal connected to the contact pad;

a second terminal connected to the reference potential;

a PNPN thyristor structure including a first P-region, a first N-region, a second P-region and a second N-region disposed in series between the first and second terminals; and

an electrode for inducing an electric field into one of the first N-region and the second P-region;

a capacitor connected between the second terminal and the electrode; and

a resistor connected between the first terminal and the electrode.

12. An input/output structure comprising:

a microelectronic device connected in circuit between a contact pad and a reference potential;

a thyristor device for protecting the microelectronic device from electrostatic discharge, the thyristor device including;

a first terminal connected to the contact pad;

a second terminal connected to the reference potential;

a PNPN thyristor structure including a first P-region, a first N-region, a second P-region and a second N-region disposed in series between the first and second terminals; and

an electrode for inducing an electric field into one of the first N-region and the second P-region, the electrode being disposed for capacitively inducing an electric field into the second P-region;

a capacitor connected between the first terminal and the electrode; and

a resistor connected between the second terminal and the electrode.

13. An input/output structure as in claim 12, in which the capacitor has a value of approximately 7×

10^-15 farads.

14. An input/output structure as in claim 12, in which the resistor has a value of approximately 60 kilo-ohms.

15. An input/output structure comprising:

a semiconductor substrate;

a contact pad formed on the substrate;

a microelectronic device which is formed on the substrate and connected in circuit between the contact pad and a reference potential;

a thyristor device for protecting the microelectronic device from electrostatic discharge, the thyristor device including;

a P-well formed in the substrate;

an N-well formed in the substrate laterally adjacent to the P-well;

a P-region formed in the N-well;

a first terminal connected to the contact pad and to the P-region;

an N-region formed in the P-well;

a second terminal connected to the reference potential and to the N-region;

first circuit means connecting the first terminal to the N-well;

second circuit means connecting the second terminal to the P-well; and

an electrode formed over a portion of the P-well between the N-region and the N-well for inducing an electric field into said portion;

a capacitor connected between the first terminal and the electrode; and

a resistor connected between the second terminal and the electrode.

16. An input/output structure as in claim 15, in which:

the first circuit means comprises a first resistor; and

the second circuit means comprises a second resistor.

17. An input/output structure as in claim 16, in which:

the first resistor comprises a P⁺ -region formed in the P-well; and

the second resistor comprises an N⁺ -region formed in the N-well.

18. An input/output structure as in claim 15, further comprising an N⁺ -region formed at an interface between the P-well and the N-well, in which:

said portion of the P-well is between the N-region and the N⁺ -region.

19. An input/output structure as in claim 18, in which:

the N-region is an N⁺ -region; and

the P-region is a P⁺ -region.

20. An input/output structure as in claim 15, in which the electrode comprises an insulated gate.

21. An input/output structure as in claim 20, in which the insulated gate comprises:

a field oxide layer; and

an electrically conductive layer formed on the field oxide layer.

22. An input/output structure as in claim 21, further comprising:

a resistor connected between the microelectronic device and the contact pad, in which;

the first terminal is connected to the contact pad.

23. An input/output structure as in claim 21, in which the field oxide layer has a thickness of approximately 8,000 Angstroms.

24. An input/output structure as in claim 20, in which the insulated gate comprises:

a thin oxide layer; and

an electrically conductive layer formed on the thin oxide layer.

25. An input/output structure as in claim 24, in which the thin oxide layer has a thickness of approximately 80 Angstroms.

26. An input/output structure as in claim 15, in which the capacitor has a value of approximately 7×

10^-15 farads.

27. An input/output structure as in claim 15, in which the resistor has a value of approximately 60 kilo-ohms.

28. An input/output structure as in claim 15, further comprising a metal interconnection layer including:

an anode section connected to the N-region and to the second terminal; and

a cathode section connected to the P-region, the first terminal and the electrode, in which;

the cathode section laterally surrounds the anode section.

29. An input/output structure comprising:

a semiconductor substrate;

a contact pad formed on the substrate;

a microelectronic device which is formed on the substrate and connected in circuit between the contact pad and a reference potential; and

a thyristor device for protecting the microelectronic device from electrostatic discharge, the thyristor device including;

a P-well formed in the substrate;

an N-well formed in the substrate laterally adjacent to the P-well;

a P-region formed in the N-well;

a first terminal connected to the contact pad and to the P-region;

an N-region formed in the P-well;

a second terminal connected to the reference potential and to the N-region;

first circuit means connecting the first terminal to the N-well;

second circuit means connecting the second terminal to the P-well; and

an electrode formed over a portion of the P-well between the N-region and the N-well for inducing an electric field into said portion;

a metal interconnection layer including;

an anode section connected to the N-region and to the second terminal; and

a cathode section connected to the P-region, the first terminal and the electrode, in which the cathode section laterally surrounds the anode section;

a capacitor connected between the first terminal and the electrode; and

a resistor connected between the second terminal and the electrode, in which;

the cathode section laterally surrounds the resistor.

30. An input/output structure as in claim 29, in which the resistor comprises an N-well resistor.

31. An input/output structure as in claim 29, in which a portion of the cathode section constitutes a plate of the capacitor.