System for interconnecting stacked integrated circuits

• US 5,682,062 A
• Filed: 06/05/1995
• Issued: 10/28/1997
• Est. Priority Date: 06/05/1995
• Status: Expired due to Term

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Gaul, Stephen Joseph
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/462,876
• Time in Patent Office: 876 Days
• Field of Search: 757/686, 757/723, 757/621, 757/81, 757/714, 757/774
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A surface mountable integrated circuit and a method of manufacture are disclosed. A wafer 110 has a die with an integrated circuit 119 in one surface of the wafer. A via 130 extends to the opposite surface. the via has a sidewall oxide 131 and is filled with a conductive material such as metal or doped polysilicon. The metal may comprise a barrier layer and an adhesion layer. The second end of the via can be fashioned as a prong 233 or a receptacle 430. Dies 335a, 335b, 335c with conductive vias are stacked on top of each other. Other dies 341, 343 are connected together with an optical coupling die 342.

Claims

1. A system of interconnected dies comprising:

two or more dies of semiconductor material, each die with first and second surfaces and with integrated circuits formed on the first surface of each die;

at least one electrical via in each die, each electrical via comprising a first open end on the first surface of the die, an elongated, open passage extending from said open end to a second open end on the second surface of the die;

an insulating layer over the surface of each electrical via;

a conductive layer over the insulating layer;

said dies being stacked so that the electrical vias of each die are axially aligned to provide contiguous portions of a continuous passageway of a plurality of axially aligned electrical vias;

a conductive material substantially contained within the continuous passageway(s) to interconnect the electrical vias of the stacked dies; and

a conductive metal layer over each integrated circuit for connecting each integrated circuit to one or more vias through said circuit.

2. The system of claim 1 wherein the vias are interconnected by electroless plating.

3. The system of claim 1 wherein the vias are interconnected by conductive paint.

4. The system of claim 1 wherein the vias are interconnected by a continuous metal wire in electrical contact with the conductive layer of each via.

5. The system of claim 1 wherein one of said die comprises a cooling die with a plurality of cooling vias disposed in a plane transverse to the electrical vias and parallel to the first and second surfaces of the cooling die, said cooling vias providing a fluid passageway for transmission of a cooling fluid.

6. A system of electrically and optically interconnected dies comprising:

a plurality of dies of semiconductor material, each die with first and second surfaces and with integrated circuits formed on the first surface of each die;

said plurality of dies including a first die with an optical transmitter, a second die with an optical transmission path, and a third die with an optical receiver, said second die disposed between the first and second dies;

said second die having an optical via aligned with the optical receiver of the first die and the optical transmitter of the second die, said second die via filled with an optical transmission material;

said first and second dies each having at least one electrical via in each die, each electrical via comprising a first open end on the first surface of the die, an elongated passage extending from said open end to a second open end on the second surface of the die;

an insulating layer over the surface of each electrical via of said first and second dies;

a conductive material in the continuous passageway(s) to interconnect the electrical vias of the stacked die, said die being stacked so that the electrical vias are aligned with each other.

7. A system for interconnecting integrated circuits comprising:

a die of semiconductor material with first and second surfaces and with integrated circuits formed on the first surface of said die;

a plurality of vias arranged in a predetermined pattern, each via comprising a first end on the first surface of the die, an elongated passage extending from said first end to a second end terminating at the second surface of said die;

a conductive material in each via, said conductive material forming an elongated body extending from a first end at the first surface of the die to the second end at the second surface of said die;

a plurality of contact pads, each pad in electrical contact with the conductive material at the second end of a via;

an interposer plate, said plate comprising an insulating material with a plurality of conductive contacts, said contacts disposed in said insulating material in another predetermined pattern corresponding to the predetermined pattern of the vias for contacting the contact pads of the die.