FPGA architecture with repeatable tiles including routing matrices and logic matrices
First Claim
Patent Images
1. An FPGA tile architecture having a plurality of tiles, each said tile comprising:
- a configurable logic block matrix, including logic circuitry;
a programmable routing matrix comprising;
routing lines extending to edges of said tile in more than one compass direction;
inter-matrix lines extending into said configurable logic block matrix and connectable to said configurable logic block matrix to provide bidirectional signal flow between said programmable routing matrix and said configurable logic block matrix; and
a plurality of programmable connectors being arranged to connect one of said inter-matrix lines to a plurality of said routing lines, whereby one of said inter-matrix lines programmably connects routing lines extending to edges of said tile in one compass direction to routing lines extending to edges of said tile in another compass direction.
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Abstract
An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.
316 Citations
75 Claims
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1. An FPGA tile architecture having a plurality of tiles, each said tile comprising:
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a configurable logic block matrix, including logic circuitry; a programmable routing matrix comprising; routing lines extending to edges of said tile in more than one compass direction; inter-matrix lines extending into said configurable logic block matrix and connectable to said configurable logic block matrix to provide bidirectional signal flow between said programmable routing matrix and said configurable logic block matrix; and a plurality of programmable connectors being arranged to connect one of said inter-matrix lines to a plurality of said routing lines, whereby one of said inter-matrix lines programmably connects routing lines extending to edges of said tile in one compass direction to routing lines extending to edges of said tile in another compass direction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62)
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63. An FPGA tile architecture comprising:
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a plurality of paired structures, each paired structure including; a configurable logic block matrix, including logic circuitry; a programmable routing matrix; a plurality of lines for connecting said configurable logic block matrix to said programmable routing matrix, wherein each of said plurality of lines provides for flow of signals from said configurable logic block matrix to said programmable routing matrix and for flow of signals from said programmable routing matrix to said configurable logic block matrix, and connects one of said lines in said programmable routing matrix to another of the lines in the programmable routing matrix; and means for connecting said programmable routing matrix to other programmable routing matrices in other paired structures, wherein said means for connecting comprises; a plurality of single length lines which connect a first programmable routing matrix to adjacent programmable routing matrices; a plurality of double length lines which connect said first programmable routing matrix to nonadjacent programmable routing matrices. - View Dependent Claims (64, 65)
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66. An FPGA tile architecture having a plurality of tiles, each said tile comprising:
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a configurable logic block matrix, including logic circuitry; a programmable routing matrix; inter-matrix lines and lines directly connecting said configurable logic block matrix to said programmable routing matrix so as to provide for signal flow from said configurable logic block matrix to said programmable routing matrix and to provide for signal flow from said programmable routing matrix to said configurable logic block matrix; and routing lines directly connecting said programmable routing matrix to programmable routing matrices in other said tiles, each said routing line being programmably connectable in said programmable routing matrix to another said routing line. - View Dependent Claims (67, 68, 69, 70, 71, 72, 73, 74)
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75. An FPGA tile architecture comprising a plurality of paired structures, each paired structure including:
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a configurable logic block matrix, including logic circuitry; a programmable routing matrix; a plurality of lines connecting said configurable logic block matrix to said programmable routing matrix, wherein each of said plurality of lines provides for flow of signals from said configurable logic block matrix to said programmable routing matrix and for flow of signals from said programmable routing matrix to said configurable logic block matrix, and connects one of said lines in said programmable routing matrix to another of the lines in the programmable routing matrix; and lines connecting said programmable routing matrix to other programmable routing matrices in other paired structures, wherein said lines comprise; a plurality of single length lines which connect a first programmable routing matrix to adjacent programmable routing matrices; and a plurality of double length lines which connect said first programmable routing matrix to nonadjacent programmable routing matrices.
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Specification