Memory cell array for digital spatial light modulator
First Claim
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1. A spatial light modulator, comprising:
- (a) an array of electrically addressable pixels;
(b) an array of memory cells arranged in rows and columns, each said memory cell being in electrical communication with at least one of said pixels; and
(c) control circuitry controlling said array of memory cells, including;
(i) a bit-line associated with each said column of said memory cells, each said bit-line for delivery pixel data to at least one said memory cell;
(ii) a write word-line associated with each said row of said memory cells, each said write word-line delivering a write signal enabling said row of said memory cells to be written with said pixel data; and
(d) a bit-line driver circuit increasing a voltage level of said pixel data before said pixel data is delivered to said memory cells, said bit-line driver circuit operating on a first power supply and said control circuitry operating on a second power supply independent from said first power supply.
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Abstract
A spatial light modulator (SLM) (20) having a pixel array (21) and a memory cell array (21a). Drivers (23c, 24b, 26, 27, 28) for the memory cell inputs permit pixels (10) of the SLM (20) to be addressed at a higher voltage than the voltage used for peripheral control circuitry (22, 23, 24). Each driver (23c, 24b, 26, 27, 28) has appropriate logic for providing an input signal to the memory cell array (21a) and a voltage translator (60) for changing the voltage level of that signal.
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Citations
15 Claims
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1. A spatial light modulator, comprising:
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(a) an array of electrically addressable pixels; (b) an array of memory cells arranged in rows and columns, each said memory cell being in electrical communication with at least one of said pixels; and (c) control circuitry controlling said array of memory cells, including; (i) a bit-line associated with each said column of said memory cells, each said bit-line for delivery pixel data to at least one said memory cell; (ii) a write word-line associated with each said row of said memory cells, each said write word-line delivering a write signal enabling said row of said memory cells to be written with said pixel data; and (d) a bit-line driver circuit increasing a voltage level of said pixel data before said pixel data is delivered to said memory cells, said bit-line driver circuit operating on a first power supply and said control circuitry operating on a second power supply independent from said first power supply. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A spatial light modulator, comprising:
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(a) an array of electrically, addressable pixels; (b) an array of memory cells arranged in rows and columns, each said memory cell being in electrical communication with at least one of said pixels; and (c) control circuitry controlling said array of memory cells, including; (i) a bit-line associated with each said column of said memory cells, each said bit-line for delivery pixel data to at least one said memory cell; (ii) a write word-line associated with each said row of said memory cells, each said write word-line delivering a write signal enabling said row of said memory cells to be written with said pixel data; and (d) a bit-line driver circuit increasing a voltage level of said pixel data before said pixel data is delivered to said memory cells, wherein a single said memory cell stores said pixel data for multiple said pixels.
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11. A spatial light modulator, comprising:
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(a) an array of electrically addressable pixels; (b) an array of memory cells arranged in rows and columns, each said memory cell being in electrical communication with at least one of said pixels; and (c) control circuitry controlling said array of memory cells, including; (i) a bit-line associated with each said column of said memory cells, each said bit-line for delivery pixel data to at least one said memory cell; (ii) a write word-line associated with each said row of said memory cells, each said write word-line delivering a write signal enabling said row of said memory cells to be written with said pixel data; and (d) a bit-line driver circuit increasing a voltage level of said pixel data before said pixel data is delivered to said memory cells, wherein each word-line is associated with multiple said rows of said pixels.
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12. A digital micromirror device, comprising:
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a mirror element array, each said mirror element being addressable via at least one address electrode and tilting in response to an address signal applied at said address electrode; a memory cell array arranged in columns and rows storing data representing a state of said address signal, each said memory cell being in electrical communication with at least one of said mirror elements via at least one said address electrode, each said memory cell having a first latch that transfers said data to a second latch in response to a transfer signal, said second latch providing said electrical communication of said address signal, to said address electrode; a bit-line associated with each said column of said memory cell array, each said bit-line delivering said data down one said column of said memory cells to at least one said memory cell, each said bit-line having a bit-line driver circuit changing a voltage level of said data before said data is delivered to said memory cell; a write word-line associated with each said row of said memory cells, each said write word-line delivering a write signal enabling one said row of said memory cells to be written with said data, each said write word-line having a word-line driver circuit changing a voltage level of said write signal; and a transfer signal driver circuit changing a voltage level of said transfer signal. - View Dependent Claims (13, 14, 15)
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Specification