Digital testing of analog memory devices

• US 5,682,352 A
• Filed: 02/08/1996
• Issued: 10/28/1997
• Est. Priority Date: 02/08/1996
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Invoice Technology Incorporated
• Inventors: So, Hock C., Wong, Sau C.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/598,485
• Time in Patent Office: 628 Days
• Field of Search: 365/201, 365/185.03, 365/45, 365/168, 324/765, 324/769, 371/21.1, 371/21.2, 371/25.1
• US Class Current: 365/201
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

An analog memory has comparison logic and a reference voltage generator built on-chip for testing of analog write and read processes. During a test, the reference voltage generator, which may be a resistor tree structure, provides a set of intermediate voltages. One of the intermediate voltages V_IN is written to a selected memory cell. The comparison logic compares other intermediate voltages V_H and V_L to an analog output signal generated by reading the selected memory cell. A digital control signal from an external digital tester selects the levels of voltages V_IN, V_H, and V_L. Typically, voltages V_H and V_L are equal V_IN ±ΔV where ΔV represents an acceptable resolution for stored analog data. If the signal from reading the selected memory cell falls within a desired range V_IN ±ΔV, an output digital result signal is set; otherwise, the test result signal is cleared. A low-cost digital tester which generates the digital control signals and observes the digital result signal can test all the circuits associated directly with write and read processes. Since the analog signals for the test are generated on-chip, the effect of noise is minimized, and a high accuracy resolution test is achieved.

Claims

1. An integrated circuit comprising:

an array of analog memory cells;

an analog write circuit coupled to the array;

an analog read circuit coupled to the array;

an analog comparator having a first input terminal and a second input terminal, the analog comparator generating an output signal having a digital state indicating whether a first input voltage is greater than a second input voltage level, a first input terminal of the analog comparator being connected to an output terminal of the read circuit when the read circuit reads a test value from the analog memory array; and

a reference voltage generator coupled to provide a first voltage to the analog write circuit during writing of the test value and a second voltage to a second input terminal of the analog comparator during reading of the test value, wherein the first voltage represents the test value.

2. The integrated circuit of claim 1, wherein the first voltage and second voltage differ by an amount that depends on a desired resolution of the analog memory cells.

3. The integrated circuit of claim 1, further comprising a second analog comparator which generates an output signal having a digital state indicating whether a first input voltage is greater than a second input voltage, wherein during reading of the test value from the memory array, a third voltage from the reference voltage generator is applied to a first input terminal of the second analog comparator and the output signal from the read circuit is applied to a second input terminal of the second analog comparator.

4. The integrated circuit of claim 3, wherein the second voltage is greater than the first voltage, and the third voltage is less than the first voltage.

5. The integrated circuit of claim 1, wherein the reference voltage generator comprises a resistor tree structure.

6. The integrated circuit of claim 5, wherein the resistor tree structure comprises:

a plurality of resistors connected in series, wherein a plurality of taps are between the resistors; and

a first multiplexer having input terminals coupled to the plurality of taps.

7. The integrated circuit of claim 6, further comprising a second multiplexer having input terminals coupled to the plurality of taps, wherein the first multiplexer selects one of the taps to supply the first voltage and the second multiplexer selects one of the taps to supply the second voltage.

8. The integrated circuit of claim 5, wherein the resistor tree structure comprises:

a plurality of resistors connected in series, wherein a plurality of taps are between the resistors; and

a plurality of shunt transistors, each shunt transistor being connected in parallel with a corresponding one of the plurality of resistors.

9. The integrated circuit of claim 8, wherein one of the plurality of taps supplies the first voltage.

10. The integrated circuit of claim 9, further comprising a multiplexer coupled to a set of the taps, wherein the multiplexer selects one of the taps to supply the second voltage.

11. The integrated circuit of claim 1, further comprising packaging which makes the reference voltage generator and the analog comparator inaccessible to a user of the integrated circuit.

12. The integrated circuit of claim 1, further comprising packaging which makes the reference voltage generator and the analog comparator accessible to a user of the integrated circuit.

13. An integrated circuit comprising:

an array of analog memory cells;

means for writing in the array a value represented by an analog input signal;

means for reading the array to generate an analog output signal representing a value read from the array; and

digitally operable test circuitry comprising;

means for using the writing means to write a test value to the array; and

means for generating a digital output signal indicating whether the analog output signal from the reading means accurately represents the test value.

14. The integrated circuit of claim 13, wherein the digitally operable test circuitry further comprises:

means for generating a first voltage and a second voltage, wherein the first voltage indicates to the writing means the test value for writing in the array; and

means for generating a first signal having a digital state indicating whether the analog output signal has a voltage level grater than the second voltage.

15. The integrated circuit of claim 14, further comprising:

means for generating a third voltage; and

means for generating a second signal having a digital state indicating whether the analog output signal has a voltage level less than the third voltage.

16. The integrated circuit of claim 15, wherein the digital output signal has a digital state indicating whether the analog output signal has a voltage level greater than the second voltage and less than the third voltage.

17. A method for testing an analog memory, comprising the steps of:

providing resistor tree structure incorporated on-chip with the analog memory;

writing to a selected memory cell in the analog memory a value represented by a first voltage from the resistor tree structure;

reading the selected memory cell to generate an analog output signal representing a value read from the selected memory cell;

comparing the analog output signal to a second voltage from the resistor tree structure; and

generating a digital signal which indicates whether the analog output signal is at a voltage level greater than the second voltage.

18. The method of claim 17, wherein the second voltage differs from the first voltage by an amount that depends on a desired resolution for the analog memory.

19. The method of claim 17, further comprising:

comparing the analog output signal to a third voltage from the resistor tree structure; and

generating a digital result signal which indicates whether the output signal is at a voltage level between the second and third voltages.

20. The method of claim 19, wherein a voltage difference between the second voltage and the first voltage is equal to a voltage difference between the third voltage and the first voltage.

21. The method of claim 19, further comprising:

varying the second and third voltage levels systematically until the digital result signal changes; and

determining the resolution of the analog memory from the second and third voltages which causes the digital result signal to change.

22. The method of claim 19, further comprising:

writing to the selected memory cell a second value represented by a fourth voltage from the resistor tree structure;

reading the selected memory cell to generate a second analog output signal;

comparing the second analog output signal to a fifth voltage and a sixth voltage from the resistor tree structure; and

generating a digital result signal which indicates whether the second analog output signal is at a voltage level between the fifth and sixth voltages.

23. The method of claim 17, wherein comparing the output signal to the second voltage comprises:

applying the output signal to a first input terminal of a first analog comparator which is incorporated on-chip with the analog memory; and

applying the second voltage to a second input terminal of the first analog comparator, wherein the first analog comparator generates the digital signal which indicates whether the analog output signal is at a voltage level greater than the second voltage.

24. The method of claim 23, further comprising:

applying a third voltage from the resistor tree structure to a first input terminal of a second analog comparator which is incorporated on-chip with the analog memory;

applying the analog output signal to a second input terminal of the second analog comparator, wherein the second analog comparator generates a digital signal which indicates whether the analog output signal is at a voltage level less than the third voltage; and

applying the digital signals from the first and second analog comparators to an AND gate to generate a digital result signal that indicates whether the analog output signal is greater than the second voltage and less than the third voltage.

25. An integrated circuit comprising:

analog circuitry which generates an analog output signal from an analog input signal;

a reference voltage generator coupled to the analog circuitry, the reference voltage generator generating a first intermediate voltage, a second intermediate voltage, and a third intermediate voltage, wherein during testing of the analog circuitry, the reference voltage generator provides to the analog circuitry the first intermediate voltage in place of the analog input signal;

a first analog comparator coupled to the analog circuitry and the reference voltage generator, wherein during testing of the analog circuitry, the first analog comparator generates a first digital signal indicating whether the analog output signal from the analog circuitry is greater than the second intermediate voltage;

a second analog comparator coupled to the analog circuitry and the reference voltage generator, wherein during testing of the analog circuitry, the second analog comparator generates a second digital signal indicating whether the analog output signal from the analog circuitry is less than the third intermediate voltage; and

a gate coupled to generate a digital result signal which is a logical AND of the first and second digital signals.