CAS recognition in burst extended data out DRAM
First Claim
Patent Images
1. A memory device having a plurality of addressable memory elements comprising:
- address circuitry adapted to operate the memory device in a burst access mode;
a first and second external address latch signals; and
a generator circuit responsive to the first and second external address latch signals to generate a control signal which transitions to an active state in response to either the first or second externaladdress latch signal that transitions to a first logic level first, and transitions to an in active state in response to either the first or second external address latch signal that transition to a second logic level first.
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Abstract
An integrated memory circuit is described which can be operated in a burst access mode. The memory circuit includes an address counter which changes column addresses in one of a number of predetermined patterns. The memory includes generator circuit for generating an internal control signal based upon external column address signals. The generator circuit detects the first active transition of the column address signals and the first inactive transition of the column address signals.
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Citations
18 Claims
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1. A memory device having a plurality of addressable memory elements comprising:
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address circuitry adapted to operate the memory device in a burst access mode; a first and second external address latch signals; and a generator circuit responsive to the first and second external address latch signals to generate a control signal which transitions to an active state in response to either the first or second external address latch signal that transitions to a first logic level first, and transitions to an in active state in response to either the first or second external address latch signal that transition to a second logic level first.
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2. A memory device having a plurality of addressable memory elements comprising:
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address circuitry adapted to operate the memory device in a burst access mode; first and second external address latch signals; and a generator circuit responsive to the first and second external address latch signals to generate a control signal which transitions to an active state in response to a first logic level transition in either of the first or second address latch signals and transitions to an in-active state in response to a second logic level transition in either of the first or second external address latch signals; the generator circuit comprises; an output circuit coupled to the plurality of external address latch signals, the output circuit being responsive to the first logic level transition in the plurality of external address latch signals; a plurality of trigger circuits coupled to the plurality of external address latch signals; and an enable circuit coupled to the plurality of trigger circuits and the output circuit, the enable circuit being responsive to the second logic level transition in the plurality of external address latch signals to disable the output circuit. - View Dependent Claims (3, 4)
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5. An integrated memory circuit comprising:
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a memory array having a plurality of addressable memory cells; a generator circuit responsive to first and second external address latch signals to generate a control signal which transitions to an active state in response to a first logic level transition in either of the first or second external address latch signals, and transitions to an in-active state in response to a second opposite logic level transition in either of the first or second external address latch signal; and an address counter to receive a first memory cell address and adapted to generate a series of memory cell addresses in response to the control signal. - View Dependent Claims (6, 7, 8, 9, 10, 17)
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11. A method of generating a control signal in a memory device, the method comprising the steps of:
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receiving a first external address latch signal; receiving a second external address latch signal; detecting a transition from a first logic state to a second logic state in either the first external address latch signal or the second external address latch signal; transitioning the control signal in response to the detection of the transition from a first logic state to a second logic state; detecting a transition from the second logic state to the first logic state in either the first external address latch signal or the second external address latch signal; and transitioning the control signal in response to the detection of the transition from the second logic state to the first logic state.
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12. A method of generating an active low control signal in a memory device, the method comprising the steps of:
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receiving a first active low column address signal; receiving a second active low column address signal; detecting a first high to low transition in either the first or second active low column address signal; transitioning the active low control signal from a high to low logic state in response to the detected high to low transition; detecting a first low to high transition in either the first or second active low column address signal; and transitioning the active low control signal from a low to a high logic state in response to the detected low to high transition.
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13. A memory device comprising:
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a plurality of addressable memory elements; first and second externally provided column address strobe (CAS) signals; and a generator circuit coupled to the first and second CAS signals, the generator circuit provides a control signal which transitions to an active state in response to a first logic level transition in either of the first or second CAS signals, and transitions to an inactive state in response to a second opposite logic level transition in either of the first or second CAS signals. - View Dependent Claims (14, 15, 16)
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18. A column address strobe signal detection circuit for use in either a first random access memory having a single column address strobe signal, or a second random access memory having multiple column address strobe signals, the column address signal detection circuit comprising:
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a select circuit for receiving an input signal indicating either the first or second random access memory device, and producing an output select signal; and a generator circuit having first and second operating states and coupled to the select circuit, in the first operating state the generator circuit produces a control signal in response to a single column address strobe signal; the generator circuit produces a control signal in the second operating state which transitions to an active state in response to a first logic level transition in one of the multiple column address strobe signals and transitions to an in-active state in response to a second logic level transition in one of the multiple of the multiple column address strobe signals.
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Specification