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CAS recognition in burst extended data out DRAM

  • US 5,682,354 A
  • Filed: 11/06/1995
  • Issued: 10/28/1997
  • Est. Priority Date: 11/06/1995
  • Status: Expired due to Term
First Claim
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1. A memory device having a plurality of addressable memory elements comprising:

  • address circuitry adapted to operate the memory device in a burst access mode;

    a first and second external address latch signals; and

    a generator circuit responsive to the first and second external address latch signals to generate a control signal which transitions to an active state in response to either the first or second externaladdress latch signal that transitions to a first logic level first, and transitions to an in active state in response to either the first or second external address latch signal that transition to a second logic level first.

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