Method and system for testing memory programming devices
First Claim
1. A method of testing a plurality of semiconductor devices which comprises the steps of:
- coupling a passflag to a recording system for each individual semiconductor device of said plurality of semiconductor devices;
sending write commands and data to a first address of said plurality of semiconductor devices in parallel;
verifying said data on the first address for each individual semiconductor device in parallel;
if said data were not successfully written into the first address for all of said plurality of semiconductor devices, repeating the steps of sending and verifying said write commands and data to the first address only for those of said plurality of semiconductor devices for which said data were not successfully written into the first address;
counting the number of repeated attempts to successfully program the first address;
if said count of repeated attempts reaches a given maximum, then rejecting any of said plurality of semiconductor devices for which said data were not successfully written into the first address as defective;
if said data are successfully written into the first address of all of said plurality of semiconductor devices, then terminating any further write attempts to the first address;
if said data are successfully written into the first address of a particular one of said plurality of semiconductor devices, setting said passflag for that particular one of said semiconductor devices to true;
if said passflag for that particular one of said semiconductor devices is set to true, terminating the sending of write commands to the first address for that particular one of said semiconductor devices; and
repeating all the preceding steps for successive addresses until a last address is reached.
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Accused Products
Abstract
A novel system and method for testing semiconductor devices has a pattern generator implementing a test signal algorithm uniquely coupled with a recording system which is an individual hardware system for each device under test. The improved pattern generator and recording system functions in conjunction with a system designed to perform parallel test and burn-in of semiconductor devices, such as the Aehr Test MTX System. The MTX can functionally test large quantities of semiconductor devices in parallel. It can also compensate for the appropriate round trip delay value for each chip select state for each device under test. This system of testing provides an effective and practical method for reducing overall test cost without sacrificing quality.
82 Citations
50 Claims
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1. A method of testing a plurality of semiconductor devices which comprises the steps of:
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coupling a passflag to a recording system for each individual semiconductor device of said plurality of semiconductor devices; sending write commands and data to a first address of said plurality of semiconductor devices in parallel; verifying said data on the first address for each individual semiconductor device in parallel; if said data were not successfully written into the first address for all of said plurality of semiconductor devices, repeating the steps of sending and verifying said write commands and data to the first address only for those of said plurality of semiconductor devices for which said data were not successfully written into the first address; counting the number of repeated attempts to successfully program the first address; if said count of repeated attempts reaches a given maximum, then rejecting any of said plurality of semiconductor devices for which said data were not successfully written into the first address as defective; if said data are successfully written into the first address of all of said plurality of semiconductor devices, then terminating any further write attempts to the first address; if said data are successfully written into the first address of a particular one of said plurality of semiconductor devices, setting said passflag for that particular one of said semiconductor devices to true; if said passflag for that particular one of said semiconductor devices is set to true, terminating the sending of write commands to the first address for that particular one of said semiconductor devices; and repeating all the preceding steps for successive addresses until a last address is reached. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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23. A system of testing semiconductor devices comprising:
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a passflag signal generator coupled to a memory programing algorithm for performing parallel tests Of devices indicating whether the semiconductor devices are defective; a first set of latches coupled to said passflag signal generator for keeping track of a state of a passflag signal generated by the passflag signal generator for each data bit of each semiconductor device; and a second latch for keeping track of a collective set of the first set of latches for each device; said algorithm comprising the steps of, for each of the semiconductor devices; sending commands and data to a first address; verifying said data at the first address; if said data were not successfully programmed onto the first address, repeating the steps of sending and verifying said commands and data onto the first address; counting the number of repeated attempts to successfully program the first address; if said count of repeated attempts reaches a given maximum, then rejecting that particular one of the semiconductor devices as defective; if said data are successfully programmed onto the first address, setting said passflag signal to true for that particular one of the semiconductor devices; if said passflag is set to true, terminating the sending of write commands to the first address for that particular one of the semiconductor devices; and repeating all the preceding steps for successive addresses until a last address is reached. - View Dependent Claims (24, 25)
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40. A method of testing a plurality of semiconductor devices which comprises the steps of:
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generating a plurality of test signals for the semiconductor devices; coupling a plurality of semiconductor devices in parallel to receive the plurality of test signals; coupling a plurality of test result readers to each of said plurality of semiconductor devices; variably compensating for appropriate round trip delay value for different groups of the semiconductor devices; generating the plurality of test signals comprising the steps of, for each of the plurality of semiconductor devices; sending commands and data to a first address; verifying said data at the first address; if said data were not successfully programmed onto the first address, repeating the steps of sending and verifying said commands and data onto the first address; counting the number of repeated attempts to successfully program the first address; if said count of repeated attempts reaches a given maximum, then rejecting that particular one of the plurality of semiconductor devices as defective; if said data are successfully programmed onto the first address, setting said passflag signal to true for that particular one of the plurality of semiconductor devices; if said passflag is set to true, terminating the sending of write commands to the first address for that particular one of the plurality, of semiconductor devices; and repeating all the preceding steps for successive addresses until a last address is reached.
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41. A semiconductor device testing apparatus, which comprises:
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a pattern generator for generating a plurality of test signals for the semiconductor devices; an interface for coupling a plurality of semiconductor devices in parallel to said pattern generator, and a plurality of test result readers connected to said interface so that one of said plurality of test result readers can be coupled to each of said plurality of semiconductor devices; where said pattern generator variably compensates for appropriate round trip delay value for different groups of the semiconductor devices. - View Dependent Claims (42, 43, 44, 45, 46, 47, 48, 49, 50)
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Specification