Parallel computer system for performing barrier synchronization by transferring the synchronization packet through a path which bypasses the packet buffer in response to an interrupt

• US 5,682,480 A
• Filed: 08/14/1995
• Issued: 10/28/1997
• Est. Priority Date: 08/15/1994
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Nakagawa, Takayuki
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Chen, Duo
• Application Number:
  US08/514,738
• Time in Patent Office: 806 Days
• Field of Search: 395/460, 395/550, 395/200.13, 395/250, 395/858, 395/872, 364/200, 364/284.1, 370/85.6
• US Class Current: 712/28
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

In a network-connected multiprocessor computer system, good cost performance and multifunctional network control is realized. In a computer system in which a plurality of processors are connected through a network, an interrupting signal line is provided in additional transmission lines. A packet is used for inter-processor communication, and a barrier synchronization packet of a fixed length is used in barrier synchronization processing. Although a barrier synchronization packet is transferred from a sending control circuit through the same transmission line for an ordinary packet, an interrupting signal is also transferred through the interrupting signal line at the same time. On the other hand, a receiving control circuit is provided with a priority control circuit in which the highest priority is given to a barrier synchronization packet, so that in response to an interrupting signal on the interrupting signal line, a barrier synchronization packet is sent to a processor without being written in a register file provided for storing an ordinary packet.

Claims

1. A parallel computer system which includes a plurality of processors and a network for transmitting packets between said processors, said network comprising:

a packet buffer for temporarily storing a packet;

a path for bypassing said packet buffer;

a signal line for supplying an interrupting signal associated with a packet; and

a selector, responsive to the interrupting signal on said signal line, for selectively outputting one of outputs from said packet buffer and;

wherein each processor sends a preferential packet onto said network and transfers an interrupting signal onto said signal line,

wherein each of said plurality of processors sends a synchronization report packet as the preferential packet onto said transmission line when said processor advances its processing to a predetermined extent, and said network transfers a synchronization establishment packet and the interrupting signal thus transferred onto said plurality of processors under the condition that said network receives synchronization report packets from said plurality of processors respectively.

2. A parallel computer system according to claim 1, wherein said network includes storage respectively corresponding to said plurality of processors so that said storage stores synchronization report packets respectively from said corresponding processors, and further includes means for generating said synchronization establishment packet when all of said storage have received said synchronization report packets respectively.

3. A parallel computer system according to claim 2, wherein said synchronization establishment packet is broadcast to the processors which have generated the synchronization report packets respectively.

4. A parallel computer system according to claim 1, wherein a preferential packet has a fixed length, and wherein said selector outputs said preferential packet from said bypassing path during transfer of said fixed length in response to an interrupting signal on said signal line.

5. A parallel computer system, comprising:

a plurality of processors and a network for transmitting a packet from each of said plurality of processors, wherein

each of said processors includes;

a sending circuit for transferring a packet to said network, and

a receiving circuit for receiving a packet from said network;

said receiving circuit of each of said processors includes;

a buffer of a plurality of stages for temporarily accumulating said packet,

a bypassing path for bypassing said buffer, and

means for making a decision as to which one of said buffer and said bypassing path is to be selected;

each of said sending and receiving circuits of each of said processors having a signal line for transmitting an interrupting signal associated with a packet;

said sending circuit includes means for transferring an interrupting signal onto said signal line with respect to a preferential packet to be transmitted with higher priority than other packets; and

said receiving circuit includes a selector, responsive to an interrupting signal on said signal line, causes output of one of the outputs from said buffer and said bypassing path,

wherein each of said plurality of processors gives an instruction to the corresponding sending circuit so as to send a synchronization report packet as a preferential packet onto said network when said each of said plurality of processors advances its processing to a predetermined extent, and

said network transfers a synchronization establishment packet and an interrupting signal onto said plurality of processors and said signal line respectively under a condition that said network receives synchronization report packets from said plurality of processors respectively.

6. A parallel computer system according to claim 5, wherein said network includes storage respectively corresponding to said plurality of processors so that said storage store synchronization report packets respectively from said corresponding processors, and wherein it is decided that said condition is established when all of said storage have received said synchronization report packets respectively.

7. A parallel computer system according to claim 6, wherein said synchronization establishment packet is broadcast to the processors which have generated the synchronization report packets respectively.

8. A parallel computer system according to claim 7, wherein said discriminating means judges whether a preferential packet transferred thereto is a synchronization report packet or any other preferential packet than a synchronization report packet, and when said preferential packet transferred thereto is any other preferential packet than a synchronization report packet, said network transfers, through said signal line, an interrupting signal associated with said packet to the processor to which said packet is to be transferred.

9. A parallel computer system according to claim 6, wherein said network includes discriminating means for discriminating a preferential packet, and when a packet transferred from a processor is a synchronization report packet, said network transfers an interrupting signal onto said signal line under the condition that said network receives synchronization report packets from said plurality of processors respectively.

10. A parallel computer system according to claim 5, wherein a preferential packet has a fixed length, and wherein said selector outputs said preferential packet from said bypassing path during transfer of said fixed length in response to an interrupting signal on said signal line.

11. A parallel computer system comprising a plurality of processors and a network for transmitting a packet from each of said plurality of processors, wherein

each of said processors includes a sending circuit for transferring a packet to said network and a receiving circuit for receiving a packet from said network;

said receiving circuit of each of said processors includes;

a buffer of a plurality of stages for temporarily accumulating said packet,

means for sending a packet transfer request to said network if said buffer is not full with packets,

a bypassing path for bypassing said buffer, and

means for making a decision as to which one of said buffer and said bypassing path is to be selected;

said sending circuit of each of said processors includes means for transmitting a packet through said network upon receiving a packet transfer request from the receiving circuit of a packet sending target;

each of said sending and receiving circuits of each of said processors having a signal line for transmitting an interrupting signal associated with a packet;

said sending circuit includes means for transferring an interrupting signal onto said signal line with respect to a preferential packet to be transmitted with higher priority than other packets; and

said receiving circuit includes a selector responsive to an interrupting signal on said signal line to output one of the outputs from said buffer and said bypassing path.

12. A method of synchronizing a plurality of processors in a parallel computer system in which said plurality of processors are connected through a network, said method comprising the steps of:

detecting that a process within one of said plurality of processors reaches a predetermined stage;

interrupting transmission of a message packet from said one of plurality of processors when said one of said plurality of processors is sending said message packet;

transmitting a report packet indicating that said one of said plurality of processors reached said predetermined stage to said network;

stopping a process within said one of said plurality of processors after transmitting said report packet to said network;

detecting in said network said report packet from said one of said plurality of processors;

interrupting reception of said message packet in said network when said network is receiving said message packet, and receiving said report packet in said network in preference to reception of said message packet;

transmitting a synchronization establishment packet representing establishment of synchronization from said network; and

receiving said synchronization establishment packet in said one of said plurality of processors to re-start the process within said one of said plurality of processors.

13. A method of synchronizing a plurality of processors in a parallel computer system according to claim 12, wherein said step of transmitting said synchronization establishment packet and said step of receiving said synchronization establishment packet includes the following substeps of:

interrupting transmission of another message packet from said network to said one of said plurality of processors when said network is sending said another message packet to said one of said plurality of processors;

transmitting said synchronization establishment packet from said network to said one of said plurality of processors;

detecting said synchronization establishment packet from said network in said one of said plurality of processors;

interrupting reception of another message packet in said one of said plurality of processors when said one of said plurality of processors is receiving said another message packet; and

receiving said synchronization establishment packet in said one of said plurality of processors in preference to said another message packet.