Computer system that maintains system wide cache coherency during deferred communication transactions

• US 5,682,516 A
• Filed: 03/01/1994
• Issued: 10/28/1997
• Est. Priority Date: 03/01/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wang, Wen Han, Sarangdhar, Nitin V., Merchant, Amit, Rhodehamel, Michael W., Fisch, Matthew A., Brayton, James M.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Peikari, James
• Application Number:
  US08/205,023
• Time in Patent Office: 1,337 Days
• Field of Search: 395/444-451, 395/473, 395/800, 395/731, 395/732, 395/856, 395/879, 364/DIG. 1, 364/DIG. 2
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/368 with decentralised access control
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete the communication transaction. Special snoop ownership and cache state transition rules maintain cache coherency and processor consistency during deferred communication transactions.

Claims

1. A computer system, comprising:

a requesting bus agent coupled to a bus, the requesting bus agent having circuitry for initiating a communication transaction on a bus;

an addressed bus agent coupled to the bus, the addressed bus agent having circuitry that senses the communication transaction on the bus, and transfers a defer indication over the bus indicating that a deferred reply transaction on the bus is required to complete the communication transaction; and

a snooping bus agent coupled to the bus, the snooping bus agent having circuitry that senses the communication transaction on the bus, and overrides the defer indication and completes the communication transaction without the deferred reply transaction if the snooping bus agent is able to complete the communication transaction as determined by the snooping bus agent performing a snoop operation.

2. The computer system of claim 1, wherein the addressed bus agent transfers the defer indication over the bus if the communication transaction requires a bus latency greater than a predetermined bus latency.

3. The computer system of claim 1, wherein the requesting bus agent, the addressed bus agent, and the bus comprise a first bus cluster, and wherein the addressed bus agent is a bus cluster interconnect agent that enables communication between the first bus cluster and a second bus cluster of the computer system.

4. The computer system of claim 3, wherein the addressed bus agent transfers the defer indication over the bus if the communication transaction requires the addressed bus agent to access the second bus cluster.

5. The computer system of claim 4, wherein the addressed bus agent includes circuitry for initiating the deferred reply transaction on the bus to complete the communication transaction.

6. The computer system of claim 5, wherein the communication transaction specifies a cache line access and wherein the addressed bus agent transfers the defer indication over the bus by asserting a defer signal on the bus during a snoop phase of the communication transaction during which a snoop operation is performed on the bus.

7. The computer system of claim 6, wherein the addressed bus agent assumes snoop ownership for the cache line access after transferring the defer indication over the bus.

8. The computer system of claim 7, wherein the addressed bus agent includes circuitry for performing the cache line access to the second bus cluster and for receiving a set of snoop results from performing the snoop operation for the cache line access from the second bus cluster.

9. The computer system of claim 8, wherein the addressed bus agent initiates the deferred reply transaction on the bus and indicates the snoop results for the cache line access on the bus during a snoop phase of the deferred reply transaction.

10. The computer system of claim 9, wherein the addressed bud agent drops snoop ownership for the cache line access after completing the deferred reply transaction on the bus.

11. The computer system of claim 8, wherein the addressed bus agent senses a subsequent communication transaction on the bus that specifies a next cache line access while the deferred reply transaction for completion of the communication transaction is pending.

12. The computer system of claim 11, wherein the addressed bus agent includes circuitry for transferring a retry indication over the bus indicating that the subsequent communication transaction requires a later retry.

13. The computer system of claim 11, wherein the addressed bus agent performs the cache line access to the second bus cluster and receives the snoop results for the cache line access from the second bus cluster, then initiates the deferred reply transaction on the bus and indicates the snoop results for the cache line access on the bus during a snoop phase of the deferred reply transaction during which a snoop operation is performed on the bus, and then drops snoop ownership for the cache line access after completing the deferred reply transaction on the bus.

14. The computer system of claim 13, wherein the addressed bus agent includes circuitry for determining whether the cache line access and the next cache line access create a snoop ownership conflict.

15. The computer system of claim 14, wherein the addressed bus agent initiates an invalidation request over the bus to invalidate the snoop results for the cache line access if the snoop ownership conflict is detected.

16. The computer system of claim 1, wherein the snooping bus agent overrides the defer indication by asserting a hit signal on the bus during the snoop phase of the communication transaction.

17. The computer system of claim 1, wherein the requesting bus agent contains a cache memory and wherein the communication transaction comprises a cache access transaction targeted for a cache line.

18. The computer system of claim 17, wherein the defer indication causes the requesting bus agent to not accept snoop ownership for the cache line during the cache access transaction if a snooping bus agent coupled to the bus does not override the defer indication.

19. The computer system of claim 18 the requesting bus agent maintains the cache line in an invalid cache state if the addressed bus agent transfers the defer indication over the bus during the deferred reply transaction.

20. The computer system of claim 18, wherein the cache access transaction comprises a read transaction targeted for the cache line.

21. The computer system of claim 20 wherein the requesting bus agent assumes the cache line in a shared cache state if the addressed bus agent transfers a cache hit signal over the bus during a snoop phase of the deferred reply transaction during which a snoop operation is performed on the bus.

22. The computer system of claim 20 wherein the requesting bus agent assumes the cache line in an exclusive cache state if the addressed bus agent does not transfer a cache hit signal over the bus during a snoop phase of the deferred reply transaction.

23. The computer system of claim 18, wherein the cache access transaction comprises a write or invalidate line transaction targeted for the cache line.

24. The computer system of claim 23, wherein the requesting bus agent reads the cache line during a data phase of the deferred reply transaction if the addressed bus agent transfers a cache hit signal over the bus during a snoop phase of the deferred reply transaction during which a snoop operation is performed on the bus.

25. The computer system of claim 23 wherein the requesting bus agent assumes the cache line in an exclusive or modified cache state if the addressed bus agent does not transfer a cache hit signal over the bus during a snoop phase of the deferred reply transaction during which a snoop operation is performed on the bus.

26. A communication method in a computer system, comprising the steps of:

initiating a communication transaction over a bus, the communication transaction specifying a cache line;

an addressed bus agent sensing the communication transaction on the bus, and transferring a defer indication over the bus to indicate that completion of the communication transaction is deferred; and

a snooping agent sensing the communication transaction on the bus, overriding the defer indication, and completing the communication transaction without a deferred reply transaction if the snooping bus agent is able to complete the communication transaction as determined by the snooping bus agent performing a snoop operation.

27. The communication method of claim 26, wherein the defer indication is transferred over the bus if the communication transaction requires a bus latency greater than a predetermined bus latency.

28. The communication method of claim 26, further comprising the step of initiating a deferred reply transaction over the bus to complete the communication transaction.

29. The communication method of claim 26, further comprising the steps of initiating a deferred reply transaction on the bus and indicating a result generated by performing a snoop operation for the cache line on the bus during the deferred reply transaction.

30. The communication method of claim 26, further comprising the steps of sensing a subsequent communication transaction on the bus that specifies a next cache line while a deferred reply transaction for completion of the communication transaction is pending.

31. The communication method of claim 30, further comprising the steps of transferring a retry indication over the bus to indicate that the subsequent communication transaction requires a later retry.

32. A computer system, comprising:

a requesting bus agent coupled to a bus, the requesting bus agent comprising a first in-order transaction queue and circuitry for initiating a communication transaction on a bus and for logging the communication transaction into the first in-order transaction queue;

an addressed bus agent coupled to the bus, the addressed bus agent having a second in-order transaction queue, and circuitry for sensing the communication transaction on the bus and for logging the communication transaction into the second in-order transaction queue, the addressed bus agent having circuitry for transferring a defer indication over the bus if the communication transaction requires a bus latency greater than a predetermined bus latency; and

a snooping bus agent coupled to the bus, the snooping bus agent having circuitry that senses the communication transaction on the bus, and overrides the defer indication and completes the communication transaction without the deferred reply transaction if the snooping bus agent is able to complete the communication transaction as determined by the snooping bus agent performing a snoop operation.

33. The computer system of claim 32, wherein the addressed bus agent includes circuitry for initiating a deferred reply transaction on the bus to complete the communication transaction.

34. The computer system of claim 33, wherein the addressed bus agent initiates the deferred reply transaction on the bus to complete the communication transaction and removes the communication transaction from the second in-order transaction queue.

35. The computer system of claim 34, wherein the requesting bus agent senses the deferred reply transaction on the bus and then removes the communication transaction from the first in-order transaction queue.

36. The computer system of claim 32, wherein the requesting bus agent contains a cache, and wherein the communication transaction specifies a cache line access.

37. The computer system of claim 36, wherein the addressed bus agent contains bridge circuitry for propagating the cache line access to a remote bus cluster.

38. The computer system of claim 37, wherein the addressed bus agent transfers the defer indication over the bus if the cache line access requires that the addressed bus agent access the remote bus cluster.