Interface component for coupling main bus of computer system to peripheral ports having windows each includes bit specifying whether operations are quiet or not quiet

• US 5,682,548 A
• Filed: 08/12/1993
• Issued: 10/28/1997
• Est. Priority Date: 08/12/1993
• Status: Expired due to Fees

• Current Assignee: Databook Incorporated
• Original Assignee: Databook Incorporated
• Inventors: Moore, Terrill M.
• Primary Examiner(s): Meky, Moustafa M.
• Application Number:
  US08/105,645
• Time in Patent Office: 1,538 Days
• Field of Search: 395/823, 395/846, 395/857, 395/858, 395/821-825, 395/828-830, 395/834, 395/835, 395/280-284, 395/800, 395/750
• US Class Current: 710/3
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a typical microprocessor based computer, many peripheral and memory devices 11, 12, 14 are connected directly to the system bus 20. Consequently, energy is wasted driving bus signals to those devices during cycles not intended for those devices. Power conservation is particularly important in portable, battery-powered systems. Credit card sized PCMCIA cards 26, 27, 28 are user-installable mass storage and I/O communication options, interfaced by an interface controller 50 interposed between the host system bus 20 and the card slots 6,7,8. The invention provides the capability for the interface controller 50 to operates a quiet bus to a plurality of, or to a single, PCMCIA card slot(s) 6, 7, 8 when configured to do so. In the quiet bus mode, address signals are not passed through to the PCMCIA card until a memory or I/O card address match qualified by appropriate control signals from the microprocessor 16 are detected, indicating a bus cycle intended for the card peripheral.

Claims

1. A computer system having a microprocessor, a main bus having a plurality of lines carrying address, data and control signals and a read/write signal indicative of a command by the microprocessor to read information at an address or to write information to an address, said main bus for carrying said signals between the microprocessor and one or more peripherals, one or more peripheral ports for receiving a peripheral, and an interface component for coupling the main bus to one or more peripheral ports, said interface component having an interface bus that is selectively operable to connect peripheral ports to the main bus, said interface bus having a plurality of lines for carrying address, data and control signals, said interface component further comprising:

means for receiving said read/write signals and other signals indicative of the type of bus cycle in progress;

means for comparing an address on the main bus with the addresses of the peripheral ports and generating a match signal indicative of a match between an address on the main bus and an address of a peripheral port;

means responsive to said match signal and said read/write and other cycle indicative signals to selectively couple the address lines of the main bus to the address lines of a peripheral port;

at least one programmable I/O window for selectively associating I/O address regions on the main bus with peripherals attached to the peripheral ports, each I/O window having in addition at least one bit, either explicitly programmable or implicitly derived by a controller from other information specified in the I/O window;

such bit specifying whether operations in the associated address region are to be quiet or not quiet;

at least one programmable memory window for selectively associating memory address regions on the main bus with peripherals attached to the peripheral ports, each memory window having in addition at least one bit, either explicitly programmable or implicitly derived by the controller from other information specified in the memory window;

such bit specifying whether operations in the associated address region are to be quiet or not quiet; and

logic means for deciding whether a cycle is to be quiet or non-quiet, based on the particular I/O windows or memory windows which are associated with the address present on the main bus.

2. The computer system of claim 1, wherein the interface component further contains means for generating a strobe signal accessible at an external pin on the interface component to selectively couple the peripheral ports to the main bus in accordance with the match and read/write signals.

3. The computer system of claim 1, wherein the interface component further comprises programmable means for normally uncoupling the peripheral port from the interface bus when the peripheral port is not addressed by the microprocessor.

4. The computer system of claim 1, wherein the interface component has a plurality of registers for holding at least one bit of data indicating whether a peripheral coupled to the interface component is to be operated in a quiet mode.

5. The computer system of claim 1, the interface component further comprising:

an interface to a bus in which I/O addresses cannot be distinguished from memory addresses until a command is received;

a means of deciding in logic conflicts which arise when a quiet memory window matches simultaneously with a non-quiet I/O window; and

a means of deciding in logic conflicts which arise when a quiet I/O window matches simultaneously with a non-quiet memory window.

6. The computer system of claim 5, where each said peripheral port is a port in compliance with PCMCIA standards.

7. The computer system of claim 1, where each said peripheral port is a port in compliance with PCMCIA standards.

8. An interface component for coupling the main bus of a computer system to one or more peripheral ports, said interface component having an interface bus that is selectively operable to connect peripheral ports to the main bus, said interface bus having a plurality of lines for carrying address, data and control signals, said interface component further comprising:

means for receiving read/write signals and other signals indicative of the type of bus cycle in progress;

means for comparing an address on the main bus with the addresses of the peripheral ports and generating a match signal indicative of a match between an address on the main bus and an address of a peripheral port;

means responsive to said match signal and said read/write and other cycle indicative signals to selectively couple the address lines of the main bus to the address lines of a peripheral port;

at least one programmable I/O window for selectively associating I/O address regions on the main bus with peripherals attached to the peripheral ports, each I/O window having in addition at least one bit, either explicitly programmable or implicitly derived by a controller from other information specified in the I/O window;

such bit specifying whether operations in the associated address region are to be quiet or not quiet;

at least one programmable memory window for selectively associating memory address regions on the main bus with peripherals attached to the peripheral ports, each memory window having in addition at least one bit, either explicitly programmable or implicitly derived by the controller from other information specified in the memory window;

such bit specifying whether operations in the associated address region are to be quiet or not quiet; and

logic means for deciding whether a cycle is to be quiet or non-quiet, based on the particular I/O windows or memory windows which are associated with the address present on the main bus.

9. The interface component of claim 8, the interface component further comprising:

an interface to a bus, in which I/O addresses cannot be distinguished from memory addresses until a command is received;

a means of deciding in logic conflicts which arise when a quiet memory window matches simultaneously with a non-quiet I/O window; and

a means of deciding in logic conflicts which arise when a quiet I/O window matches simultaneously with a non-quiet memory window.

10. The interface component of claim 9, where each said peripheral port is a port in compliance with PCMCIA standards.

11. The interface component of claim 8, where each said peripheral port is a port in compliance with PCMCIA standards.