Enhanced mobility MOSFET device and method

• US 5,683,934 A
• Filed: 05/03/1996
• Issued: 11/04/1997
• Est. Priority Date: 09/26/1994
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Candelaria, Jon J.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/642,820
• Time in Patent Office: 550 Days
• Field of Search: 437/41, 437/44, 437/100, 437/110, 437/134
• US Class Current: 438/151
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: Y10S 438/931 Silicon carbide semiconductor

Abstract

An enhanced mobility MOSFET device (10) comprises a channel layer (12) formed on a monocrystalline silicon layer (11). The channel layer (12) comprises an alloy of silicon and a second material with the second material substitutionally present in silicon lattice sites at an atomic percentage that places the channel layer (12) under a tensile stress.

Claims

1. A method for making an enhanced mobility semiconductor device comprising the steps of:

forming a carrier transport region on a first conductivity type monocrystalline silicon layer, wherein the carrier transport region comprises an alloy of the silicon and a second semiconductor material, and wherein the second semiconductor material is substitutionally present in the carrier transport region lattice sites at an atomic percentage that places the carrier transport region under tensile stress compared to the first conductivity type monocrystalline silicon layer, and wherein the carrier transport region has a bandgap narrower than the monocrystalline silicon layer;

forming an epitaxial semiconductor layer over the carrier transport region;

forming a gate dielectric layer on the epitaxial semiconductor layer above a portion of the carrier transport layer;

forming a control electrode on the gate dielectric layer;

forming a source region of a second conductivity type extending through the epitaxial semiconductor layer at least into the carrier transport region; and

forming a drain region of the second conductivity type extending through the epitaxial semiconductor layer at least into the carrier transport region, wherein the portion of the carrier transport region is between the source region and the drain region.

2. The method of claim 1 wherein the step of forming the carrier transport region includes forming a channel layer comprising a Si_1-x C_x alloy, wherein X is less than or equal to 0.02.

3. The method of claim 2 wherein the step of forming the carrier transport region includes forming a channel layer having a thickness on an order of 1000 angstroms, wherein X is in a range from 0.005 to 0.016, and wherein the step of forming the epitaxial semiconductor layer includes forming an epitaxial silicon layer having a thickness on an order of 50 angstroms, and wherein the step of forming the gate dielectric layer includes forming a gate oxide layer comprising a silicon oxide having a thickness in a range from 30 to 125 angstroms.

4. The method of claim 1 further comprising the step of forming an insulating layer below the monocrystalline silicon layer.

5. The method of claim 1 further comprising the step of forming a modulation doped layer within the monocrystalline silicon layer.

6. A process for forming an enhanced mobility semiconductor MOSFET structure including the steps of:

forming a channel layer comprising a Si_1-x C_x alloy on a monocrystalline silicon layer of a first conductivity type, wherein carbon is present in the channel layer in substitutional lattice sites so that the channel layer is under tensile stress, and wherein the channel layer has a bandgap narrower than the monocrystalline silicon layer;

forming an epitaxial silicon layer on the channel layer;

forming a source region of a second conductivity type extending through the epitaxial silicon layer and at least into the channel layer;

forming a drain region of the second conductivity type extending through the epitaxial silicon layer and at least into the channel layer, wherein part of the channel layer separates the source region from the drain region;

forming a gate dielectric layer on the epitaxial silicon layer between the source region and the drain region; and

forming a gate electrode on the gate dielectric layer.

7. The process of claim 6 wherein the step of forming the channel layer includes forming the channel layer wherein X is less than or equal to 0.02.

8. The process of claim 7 wherein the step of forming the channel layer includes forming the channel layer wherein X is between 0.005 and 0.016.

9. The process of claim 6 wherein the step of forming the gate dielectric layer includes forming the gate dielectric layer having a thickness in a range from about 30 to 125 angstroms.

10. The process of claim 6 further comprising the step of forming an insulating region below the monocrystalline silicon layer.

11. The process of claim 6 wherein the step of forming the channel layer includes forming the channel layer on the monocrystalline silicon layer, wherein the monocrystalline silicon layer includes a modulation layer disposed within the monocrystalline silicon layer, and wherein a portion of the monocrystalline silicon layer separates the modulation layer from the channel layer, and wherein the modulation layer is of the second conductivity type, and wherein the modulation layer has a dopant concentration that is higher than dopant concentration in the monocrystalline silicon layer.

12. The process of claim 6 wherein the step of forming the channel layer includes forming the channel layer on the monocrystalline silicon layer, wherein the monocrystalline silicon layer has a thickness on an order of 1000 angstroms, the channel layer has a thickness on an order of 100 angstroms, and the epitaxial silicon layer has a thickness on an order of 50 angstroms.

13. A method for forming an enhanced mobility semiconductor device comprising the steps of:

providing a monocrystalline silicon layer of a first conductivity type;

forming a carrier transport region on the monocrystalline silicon layer, wherein the carrier transport region comprises an alloy of silicon and a second material, and wherein the carrier transport region is under tensile stress, and wherein the carrier transport region has a bandgap narrower than the monocrystalline silicon layer;

forming a source region of a second conductivity type extending into the carrier transport region;

forming a drain region of the second conductivity type extending into the carrier transport region; and

forming an electrically insulated control electrode over the carrier transport region, wherein the control electrode is disposed between the source region and the drain region.

14. The method of claim 13 further comprising the step of forming a silicon epitaxial layer disposed between the carrier transport region and the electrically insulated control electrode, wherein the source region and the drain region extend through the epitaxial layer into at least the carrier transport region.

15. The method of claim 13 wherein the step of forming the carrier transport region includes forming a carrier transport region comprising a Si_1-x C_x alloy.

16. The method of claim 15 wherein the step of forming the carrier transport region includes forming a carrier transport region comprising a Si_1-x C_x alloy, and wherein X is less than or equal to 0.02.

17. The method of claim 13 wherein the step of providing the monocrystalline silicon layer includes providing the monocrystalline silicon layer having an insulating layer disposed below the monocrystalline silicon layer.

18. The method of claim 13 wherein the step of forming the source region includes forming the source region extending through the carrier transport region into the monocrystalline silicon layer, and wherein the step of forming the drain region includes forming the drain region extending through the carrier transport region into the monocrystalline silicon layer.

19. The method of claim 13 wherein the step of providing the monocrystalline silicon layer includes providing the monocrystalline silicon layer having a modulation doping layer disposed within the monocrystalline silicon layer, and wherein a portion of the monocrystalline silicon layer separates the modulation doping layer from the carrier transport region, and wherein the modulation doping layer is of the second conductivity type and has a dopant concentration higher than the monocrystalline silicon layer.