Vertical precharge structure for DRAM

• US 5,684,313 A
• Filed: 02/20/1996
• Issued: 11/04/1997
• Est. Priority Date: 02/20/1996
• Status: Expired due to Fees

• Current Assignee: Donald M. Kenney
• Original Assignee: Donald M. Kenney
• Inventors: Kenney, Donald M.
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): Cao, Phat X.
• Application Number:
  US08/603,832
• Time in Patent Office: 623 Days
• Field of Search: 257/296, 257/304, 257/307, 257/303, 365/182, 365/149, 437/228
• US Class Current: 257/296
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A DRAM one device cell and an associated precharge circuit are integrated together in a novel structure having an area of only four square features. The structure also provides physical and electrical separation between adjacent cells along a direction parallel to the DRAM word lines. The DRAM bit line length per bit is reduced by 50% relative to a conventional planar integrated structure disclosed elsewhere. As a result, bit line capacitance is also substantially reduced, and the effectiveness of a precharge technique for reduction of DRAM power consumption is enhanced by the dense novel structure.

Claims

1. An array of dynamic random access memory cells of a chosen cell structure formed on a semiconductor substrate, said cells arranged in rows and columns, each said cell including a first PN junction utilized as a storage node junction, a second PN junction utilized as a bit line junction, and a first transistor channel region located between said first PN junction and said second PN junction, and, a first word line in each said column disposed so as to gate said first transistor channel regions, the improvement comprising:

a. trenches in said semiconductor substrate disposed adjacent the first PN junctions, and

b. a third PN junction disposed adjacent each said trench and physically separated from the first and second PN junctions, and

c. a second word line along each column disposed substantially parallel to said first word line and having no contact to the first PN junctions, said second word lines further disposed in said trenches so as to gate second transistor channel regions extending from the first PN junctions to said third PN junction, the second word lines extending at least from the first PN junctions to the third PN junction.

2. An array according to claim 1 in which the trench separates said cells and said second transistor channel regions disposed adjacent a first trench sidewall from the cells and second transistor channel regions disposed adjacent a second trench sidewall.

3. A memory array according to claim 2 in which a second word line disposed adjacent said first trench sidewall isolates the cells disposed adjacent the first trench sidewall from the cells and second transistor channel regions disposed adjacent said second trench sidewall.

4. An array of dynamic random access memory cells of a chosen cell structure formed on a semiconductor substrate, said cells arranged in rows and columns, each said cell including a first PN junction utilized as a storage node junction, a second PN junction utilized as a bit line junction, and a first transistor channel region located between said first PN junction and said second PN junction, and, a first word line in each said column disposed so as to gate said first transistor channel regions, the improvement comprising:

a. trenches in said semiconductor substrate disposed adjacent the first PN junctions, and

b. a third PN junction disposed adjacent each said trench and physically separated from the first and second PN junctions, and

c. second transistor channel regions disposed on sidewalls of said trenches, said second transistor channel regions having a length dimension extending along a trench sidewall from a first PN junction to said third PN junction, a second word line along each column disposed substantially parallel to said first word lines and having no contact to the first PN junctions, said second word lines further disposed in said trenches so as to gate along the entire said length dimension of the second transistor channel regions.

5. An array according to claim 4 in which the trench separates said cells and said second transistor channel regions disposed adjacent a first trench sidewall from the cells and second transistor channel regions disposed adjacent a second trench sidewall.

6. A memory array according to claim 5 in which a second word line disposed adjacent said first trench sidewall isolates the cells disposed adjacent the first trench sidewall from the cells and second transistor channel regions disposed adjacent said second trench sidewall.