Semiconductor device having transistor pair

• US 5,684,320 A
• Filed: 07/03/1995
• Issued: 11/04/1997
• Est. Priority Date: 01/09/1991
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kawashima, Shoichiro
• Primary Examiner(s): MEIER, STEPHEN D
• Application Number:
  US08/497,843
• Time in Patent Office: 855 Days
• Field of Search: 257/66, 257/351, 257/369, 257/57, 257/288, 257/364
• US Class Current: 257/351
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A semiconductor device has a plurality of transistor pairs. Each transistor pair includes a p-channel current path having a pair of p-type current terminal regions arranged by sandwiching a high resistivity first channel region and an n-channel current path having a pair of n-type current terminal regions arranged by sandwiching a high resistivity second channel region. The first channel region and the second channel region exert electric fields on each other by their intrinsic charges and are adjacently arranged so as to serve as a gate. A semiconductor memory device includes a memory element formed by first and second thin film semiconductor layers each including a semiconductor region of the first conductivity type and a semiconductor region of the second conductivity type sandwiching a channel region. A backgate is disposed in a faced relation to the channel region of one of the first and second thin film semiconductor layers which are laminated one atop the other. Alternatively, the memory element is formed by a lamination of four such thin film semiconductor layers and includes a gate for writing disposed opposite the channel region of one of the thin film semiconductor layers which forms one end of the lamination, and an element for reading disposed opposite the channel region of one of the thin film semiconductor layers which forms the other end of the lamination.

Claims

1. A semiconductor memory device comprising a memory element comprising:

a first thin film semiconductor layer having a semiconductor region of a first conductivity type, a semiconductor region of a second conductivity type and a channel region sandwiched between said semiconductor region of the first conductivity type and said semiconductor region of the second conductivity type;

a second thin film semiconductor layer having a semiconductor region of the first conductivity type, a semiconductor region of the second conductivity type and a channel region sandwiched between said semiconductor region of the first conductivity type and said semiconductor region of the second conductivity type;

said first and second layers are laminated one atop the other in such a manner that said semiconductor regions having the first conductivity type of said two thin film semiconductor layers are opposed each other and said semiconductor regions having the second conductivity type of said two thin film semiconductor layers are opposed each other;

a gate for writing which is disposed in a facing relation with said channel region of one of said first and second thin film semiconductor layers; and

a third thin film semiconductor layer which is disposed between said one of said first and second thin film semiconductor layers and said gate for writing, said third thin film semiconductor layer including a semiconductor region of the first conductivity type and a semiconductor region of the second conductivity type with a channel region sandwiched therebetween.

2. The device according to claim 1, wherein said first thin film semiconductor layer and said second thin film semiconductor layer form a holding layer for holding a charge and said third thin film semiconductor layer forms a buffer layer between said gate for writing and said holding layer.

3. The device according to claim 1, wherein said semiconductor region of the first conductivity type and said semiconductor region of the second conductivity type of said third thin film semiconductor layer are located respectively in a faced relation to said semiconductor region of the first conductivity type and said semiconductor region of said first or said second thin film semiconductor layer forming said holding layer.

4. A semiconductor memory device comprising a memory element comprising:

a first thin film semiconductor layer having a semiconductor region of a first conductivity type, a semiconductor region of a second conductivity type and a channel region sandwiched between said semiconductor region of the first conductivity type and said semiconductor region of the second conductivity type;

a second thin film semiconductor layer having a semiconductor region of the first conductivity type, a semiconductor region of the second conductivity type and a channel region sandwiched between said semiconductor region of the first conductivity type and said semiconductor region of the second conductivity type;

said first and second layers are laminated one atop the other;

an element for reading which is located in a facing relation to said channel region of one of said first and said second thin film semiconductor layers; and

a third thin film semiconductor layer which is disposed between said one of said first and second thin film semiconductor layers and said element for reading, said third thin film semiconductor layer including a semiconductor region of the first conductivity type and a semiconductor region of the second conductivity type with a channel region sandwiched therebetween.

5. The device according to claim 4, wherein said first thin film semiconductor layer and said second thin film semiconductor layer form a holding layer for holding a charge and said third thin film semiconductor layer forms a buffer layer between an element for reading and said holding layer.

6. The device according to claim 4, wherein said semiconductor region of the first conductivity type and said semiconductor region of the second conductivity type of said third thin film semiconductor layer are located respectively in a faced relation to said semiconductor region of the first conductivity type and said semiconductor region of said first or said second thin film semiconductor layer forming said holding layer.

7. A semiconductor memory device comprising a memory element comprising:

a first thin film semiconductor layer having a semiconductor region of a first conductivity type, a semiconductor region of a second conductivity type and a channel region sandwiched between said semiconductor region of the first conductivity type and said semiconductor region of the second conductivity type;

a second thin film semiconductor layer having a semiconductor region of the first conductivity type, a semiconductor region of the second conductivity type and a channel region sandwiched between said semiconductor region of the first conductivity type and said semiconductor region of the second conductivity type;

said first and second layers are laminated one atop the other;

a gate for writing which is located in a facing relation to said channel region of one of said thin film semiconductor layers;

an element for reading which is located in a faced relation to said channel region of the other one of said thin film semiconductor layers;

a third thin film semiconductor layer between said one of said first and second thin film semiconductor layers and said gate for writing, said third thin film semiconductor layer including a semiconductor region of the first conductivity type and a semiconductor region of the second conductivity type a channel region sandwiched therebetween; and

a fourth thin film semiconductor layer which is disposed between the other one of said first and second thin film semiconductor layers and said element for reading, said fourth thin film semiconductor layer including a semiconductor region of the first conductivity type and a semiconductor region of the second conductivity type with a channel region sandwiched therebetween.

8. A semiconductor memory device, comprising:

at least four thin film semiconductor layers, each including a semiconductor region of a first conductivity type and a semiconductor region of the second conductivity type with a channel region sandwiched therebetween, said layers are laminated one atop the other into a lamination with insulator layers interposed therebetween with said semiconductor regions of the same conductivity type facing each other;

a gate for writing disposed in an opposing relation to said channel region of one of said thin film semiconductor layers which forms a first end of said lamination with an insulator layer interposed between said gate for writing and said thin film semiconductor layer forming the first end of said lamination; and

an element for reading disposed in an opposing relation to said channel region of one of said thin film semiconductor layers which forms a second end of said lamination with an insulator layer interposed between said element for reading and said thin film semiconductor layer forming the second end of said lamination.

9. The device according to claim 8, further comprising insulator films between said layers and a gate insulator film between said thin film semiconductor layer of the first end and said gate for writing with said gate insulator film being thicker than said insulator films between said respective thin film semiconductor layers.

10. The device according to claim 8, further comprising:

wirings supplying predetermined potentials and connected to said semiconductor regions of the first conductivity type and said semiconductor regions of the second conductivity type constituting said thin film semiconductor layers; and

control means for supplying a selected voltage to each one of said semiconductor regions of the first and the second conductivity types which form said thin film semiconductor layers individually, said control means being connected to said wirings, and

wherein said element for reading is formed by a field effect transistor (FET) formed within a substrate.