Semiconductor device having an input protection circuit

• US 5,684,321 A
• Filed: 06/07/1995
• Issued: 11/04/1997
• Est. Priority Date: 11/10/1994
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Okamura, Junichi
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): Wallace, Valencia Martin
• Application Number:
  US08/481,828
• Time in Patent Office: 881 Days
• Field of Search: 257/355, 257/356, 257/357, 257/358, 257/379
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

An input protection circuit is formed on a semiconductor substrate. A resistive element of an impurity diffusion region is electrically isolated from a main region of the substrate by a first double well structure. A bipolar transistor is connected to the resistive element which is electrically isolated from the main region of the substrate by a second double well structure. An input pad is connected to the bipolar transistor.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

a first terminal;

a second terminal;

a first outer well of a second conductivity type formed in said semiconductor substrate;

a first inner well of the first conductivity type formed in said first outer well;

a second outer well of a second conductivity type formed in said semiconductor substrate;

a second inner well of the first conductivity type formed in said second outer well;

a resistive element comprising a diffusion region of the second conductivity type formed in said first inner well; and

an input protection circuit element having at least one PN junction formed in said second inner well, wherein said resistive element and said input protection circuit element are connected in series between said first terminal and said second terminal and said resistive element is electrically isolated from said PN junction.

2. The semiconductor device according to claim 1, wherein said first terminal is a signal input pad, said second terminal is a constant power supply pad, and said resistive element is directly connected to said first terminal.

3. The semiconductor device according to claim 1, wherein said first terminal is a signal input pad, said second terminal is a constant power supply pad, and said resistive element is directly connected to said second terminal.

4. An input protection circuit formed on a semiconductor substrate, comprising:

a resistive element comprising an impurity diffusion region electrically isolated from a main body of said semiconductor substrate by a first double well arrangement;

a bipolar transistor connected to said resistive element, said bipolar transistor being electrically isolated from said main body of said semiconductor substrate by a second double well arrangement, wherein said first double well arrangement is independent of said second double well arrangement; and

p1 an input terminal connected to said bipolar transistor.

25. The semiconductor device according to claim 4, wherein said bipolar transistor is a lateral-type bipolar transistor.

5. An input protection circuit formed on a semiconductor substrate for protecting internal circuits, comprising:

a first terminal;

a second terminal;

at least one PN junction, said PN junction being electrically separated from a main body of said semiconductor substrate; and

a resistive element comprising an impurity diffusion region which is electrically separated from the main body of said semiconductor substrate, wherein said PN junction and said resistive element are connected in series between said first terminal and said second terminal and said resistive element is electrically isolated from said PN junction.

6. The input protection circuit according to claim 5, wherein said internal circuits comprise:

a plurality of memory cells arranged in matrix, a plate electrode of said memory cells being formed under a surface of said semiconductor substrate, and said plate electrode and said resistive element being electrically isolated from each other.

7. A semiconductor device, comprising:

a signal input terminal for receiving an externally supplied input signal;

an input protection circuit connected to said signal input terminal;

a reference voltage generation circuit for generating a constant reference voltage; and

a comparison circuit connected to said input protection circuit and said reference voltage generation circuit for comparing the input signal and the reference voltage,

wherein said reference voltage generation circuit and said input protection circuit are electrically isolated by a double well having at least two PN junctions.

8. The semiconductor device according to claim 7, wherein said input protection circuit comprises a bipolar transistor connected to said signal input terminal and a resistive element connected to said bipolar transistor, and said bipolar transistor and said resistive element are formed in separate double wells electrically isolated from each other.

9. A semiconductor device, comprising:

a first pad;

a second pad;

a third pad;

a first bipolar transistor having a base, a first current terminal connected to said second pad, and a second current terminal connected to said first pad;

a second bipolar transistor having a base, a first current terminal connected to said second pad, and a second current terminal connected to said third pad;

a resistive element separated from the first and the second bipolar transistors and electrically isolated from the current terminals of said first and second bipolar transistors by a double well structure, said resistive element having a first terminal connected to the bases of said first and second bipolar transistors and a second terminal connected to said third pad.

10. The semiconductor device according to claim 9, wherein said resistive element comprises an impurity diffusion region.

11. The semiconductor device according to claim 9, wherein the first current terminals of said first and second bipolar transistors are connected to a gate of a MOS transistor of an internal circuit.

21. The semiconductor device according to claim 10, wherein said impurity diffusion region comprises a predetermined number of turns, said turns defining folds in the impurity diffusion region, wherein a resistance of said resistive element is determined by a length of the impurity diffusion region, said length of said impurity diffusion region being varied by a number of folds and turns.

12. A semiconductor device comprising:

a first pad;

a second pad;

a third pad;

a first bipolar transistor having a base connected to said third pad, a first current terminal, and a second current terminal connected to said first pad;

a second bipolar transistor having a base connected to said third pad, a first current terminal, and a second current terminal connected to said third pad;

a resistive element separated from said first and second bipolar transistors and electrically isolated from the current terminals of said first and second bipolar transistors by a double well structure, said resistive element having a first terminal connected to the first current terminals of said first and second bipolar transistors and a second terminal connected to said second pad.

13. The semiconductor device according to claim 12, wherein said resistive element comprises an impurity diffusion region.

14. The semiconductor device according to claim 12, wherein the first current terminals of said first and second bipolar transistors are connected to a gate of a MOS transistor of an internal circuit.

22. The semiconductor device according to claim 13, wherein said impurity diffusion region comprises a predetermined number of turns, said turns defining folds in the impurity diffusion region, wherein a resistance of said resistive element is determined by a length of the impurity diffusion region, said length of said impurity diffusion region being varied by a number of folds and turns.

15. A semiconductor device, comprising:

a plurality of pads arranged linearly;

a plurality of input protection elements arranged linearly alongside said pads;

a signal bus arranged along side said input protection elements; and

a resistive element connected to and shared by each of said plurality of input protection elements.

16. The semiconductor device according to claim 15, wherein input protection elements are bipolar transistors, each provided for a corresponding one of said pads.

17. The semiconductor device according to claim 15, wherein said resistive element comprises an impurity diffusion region.

23. The semiconductor device according to claim 17, wherein said impurity diffusion region comprises a predetermined number of turns, said turns defining folds in the impurity diffusion region, wherein a resistance of said resistive element is determined by a length of the impurity diffusion region, said length of said impurity diffusion region being varied by a number of folds and turns.

18. A semiconductor device, comprising:

first, second, third, and fourth rectangular core blocks each having a plurality of memory cells arranged in matrix;

a first buffer block arranged between said first and second rectangular core blocks, said first buffer block having a plurality of address pads and first input protection circuits arranged linearly; and

a second buffer block arranged between said third and fourth rectangular core blocks, said second buffer block having a plurality of data I/O pads and second input protection circuits arranged linearly, wherein

said first buffer block includes a first resistive element electrically isolated from said first, second, third, and fourth core blocks by a first double well; and

said second buffer block includes a second resistive element electrically isolated from the first, second, third, and fourth core blocks by a second double well.

19. The semiconductor device according to claim 18, wherein said resistive element comprises an impurity diffusion region.

20. The semiconductor device according to claim 18, further comprising:

a reference voltage generating circuit arranged between said first and third core blocks, said reference voltage generating circuit being electrically isolated from said first and second resistive elements by said first and second double wells.

24. The semiconductor device according to claim 19, wherein said impurity diffusion region comprises a predetermined number of turns, said turns defining folds in the impurity diffusion region, wherein a resistance of said resistive element is determined by a length of the impurity diffusion region, said length of said impurity diffusion region being varied by a number of folds and turns.