Clock signal generator

• US 5,684,418 A
• Filed: 12/22/1995
• Issued: 11/04/1997
• Est. Priority Date: 12/26/1994
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yanagiuchi, Hiroshi
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): LAM, TUAN THIEU
• Application Number:
  US08/577,812
• Time in Patent Office: 683 Days
• Field of Search: 327/99, 327/115, 327/116, 327/117, 327/119, 327/120, 327/121, 327/295, 327/298, 327/105, 327/113, 377/47, 377/48
• US Class Current: 327/99
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: H03B 19/00 Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source transference of modulation from one carrier to another H03D7/00
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A clock signal generator can prevent unnecessary power consumption and can lower the power consumption of a system or a chip as a whole. A clock generator has a plurality of multipliers having variable multiplying factors and multiplying a single input reference clock signal by a designated multiplying factor. A plurality of frequency dividers have variable divide factors and divide a clock signal by a designated dividing factor. A clock selector selects a clock signal which has a required frequency according to a status signal STS from each of the functional locks from among the clock signals having a plurality of frequencies generated by the clock generator. The clock selectors stops the operation of the multipliers or the frequency dividers which are generating unused frequencies by switching clock signals.

Claims

1. A clock signal generator, comprising:

a clock generator having at least a first multiplier, which has a first variable multiplying factor, for multiplying an input reference clock signal by the first variable multiplying factor to generate a first clock signal of a first frequency and a second multiplier, which has a second variable multiplying factor, for multiplying the input reference clock signal by the second variable multiplying factor to generate a second clock signal of a second frequency;

a clock selector for receiving a status signal specifying a desired clock frequency for a functional block, for supplying the functional block with the first clock signal when the desired frequency equals the first frequency, and for supplying the functional block with the second clock signal when the desired frequency equals the second frequency, and for supplying the clock generator with an operation control signal, said operation control signal for stopping the first multiplier when the desired frequency is the second frequency and for stopping the second multiplier when the desired frequency is the first frequency.

3. A clock signal generator according to claim 1, wherein said second multiplier comprises a frequency divider, the second variable multiplying factor comprises a variable dividing factor, and said frequency divider includes:

a pulse signal generator generating a pulse signal which has a predetermined pulse width based on the input reference clock signal;

a delay circuit receiving the pulse signal generated by the pulse signal generator and delaying the pulse signal by a natural number designating the variable dividing factor; and

an output circuit receiving the delayed pulse signal from the delay circuit and outputting the second clock signal which has a pulse width proportional to a delay value of the delay circuit.

4. The clock signal generator as set forth in claim 1, wherein the clock generator comprises a plurality of multipliers, including the first and second multipliers, for multiplying the input reference clock signal by a respective plurality of variable multiplying factors and a plurality of dividers for dividing the input reference clock signal by a respective plurality of variable dividing factors.

5. A clock signal generator according to claim 4, wherein said clock selector comprises:

a plurality of latch groups each latching a plurality of status signals output from a plurality of functional blocks, each of the status signals designating a desired clock signal for the respective functional block;

a plurality of selectors each selecting the desired clock signal which has a desired frequency from among clock signals output from the multipliers and the frequency dividers of the clock generator; and

the clock selector for adjusting the clock signals selected by each of the plurality of selectors according to the status signals latched by the latch groups and for generating operation control signals for the multipliers and frequency dividers, the operation control signals enabling only the multipliers and the frequency dividers generating clock signals designated by the status signals and stopping multipliers and the frequency dividers that generate clock signals not used by any of the functional blocks.

6. A clock signal generator according to claim 1, further comprising an inhibit circuit for inhibiting the stopping of the first multiplier when a second functional block generates a second status signal specifying the first frequency as the desired frequency for the second functional block and for inhibiting the stopping of the second multiplier when the second status signal specifies the second frequency as the desired frequency for the second functional block.

7. The clock signal generator as set forth in claim 1, wherein the second multiplier multiplies the input reference clock signal by the second variable multiplying factor which has a value less than 1.

8. The clock signal generator as set forth in claim 1, wherein the clock selector receives a plurality of status signals specifying desired clock frequencies for a plurality of functional blocks and for supplying the functional blocks with the first clock signal when their respective status signals designate the first frequency as the desired frequency and for supplying the functional blocks with the second clock signal when their respective status signals designate the second frequency as the desired frequency.

9. The clock signal generator as set forth in claim 1, wherein the first multiplier receives the input reference clock signal and multiplies the input reference clock signal by the first variable multiplying factor and the second multiplier receives an output from the first multiplier and multiplies the output from the first multiplier by a third variable multiplying factor, the third variable multiplying factor being equal to a quotient of the second variable multiplying factor by the first variable multiplying factor.

2. A clock signal generator, comprising:

a clock generator having at least one multiplier, which has a variable multiplying factor, for multiplying an input reference clock signal by a designated multiplying factor and at least one frequency divider, which has a variable dividing factor, for dividing the input reference clock signal by a designated dividing factor;

a clock selector for selecting a desired clock signal having a desired frequency from outputs of the at least one multiplier and the at least one divider and for supplying the desired clock signal to a functional block, the clock selector receiving a status signal from the functional block which specifies the desired frequency;

wherein said multiplier comprises;

a first pulse signal generator receiving the input reference clock signal and generating a first pulse signal which has a predetermined pulse width according to the input reference clock signal;

a decision circuit specifying a delay value according to a first natural number, the first natural number determining the designated multiplying factor;

a delay circuit delaying the first pulse signal according to the delay value to form a delayed pulse signal;

an output circuit switching an output level between a first level and a second level at each input of the first pulse signal or a second pulse signal;

a second pulse signal generator receiving the delayed pulse signal from the delay circuit and generating the second pulse signal and a third pulse signal which have a complementary relationship with each other, the second pulse signal generator generating the second and third pulse signals using the first natural number designating the multiplying factor and supplying the second pulse signal to the delay circuit and the output circuit; and

a pulse phase adjusting circuit comparing the first pulse signal generated by the first pulse signal generator with the third pulse signal and feeding back a result of the comparison to the delay circuit to adjust a phase of the delayed pulse signal.

10. A clock signal generator, comprising:

a clock generator having a plurality of multipliers, each having a variable multiplying factor, for multiplying an input reference clock signal by designated multiplying factors and a plurality of frequency dividers, each having a variable dividing factor, for dividing the input reference clock signal by designated dividing factors;

a clock selector for selecting desired clock signals having desired frequencies from outputs of the multipliers and dividers and for supplying the desired clock signals to a plurality of functional blocks, the clock selector receiving status signals from the functional blocks which specify the desired frequencies;

wherein the clock selector includes a clock selecting circuit for receiving the status signals and for generating operation control signals, said operation control signals supplied to the plurality of multipliers and the plurality of dividers and are for enabling the multipliers and dividers which generate any one of the desired clock signals and for stopping the multipliers and dividers that do not generate any one of the desired clock signals.

11. The clock signal generator as set forth in claim 10, wherein the clock selecting circuit comprises a delay circuit for delaying the stopping of each multiplier and divider until a subsequent clock cycle and for preventing each multiplier and divider from being stopped when the status signal received at the subsequent clock cycle from any one of the functional blocks designates the multiplier or the divider.

12. The clock signal generator as set forth in claim 10, wherein the designated multiplying factor is unique for each multiplier and the designated dividing factor is unique for each divider.

13. The clock signal generator as set forth in claim 10, wherein the clock selector comprises a plurality of latch groups with each latch group associated with a respective functional block, each latch group receiving the status signals from the respective functional block and latching the desired clock signal for the respective functional block out of the clock signals from all of the multipliers and dividers.

14. The clock signal generator as set forth in claim 13, wherein the clock selecting circuit comprises a plurality of clock selecting circuits with each clock selecting circuit associated with a respective latch group and functional block, each clock selecting circuit supplying an enable signal to the multiplier or divider generating the desired clock signal for the respective functional block.

15. The clock signal generator as set forth in claim 14, wherein each multiplier or divider is disabled unless the multiplier or divider receives the enable signal from one of the clock selecting circuits.