Erasable and programmable single chip clock generator

• US 5,684,434 A
• Filed: 10/30/1995
• Issued: 11/04/1997
• Est. Priority Date: 10/30/1995
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Mann, Eric N., Torode, John Q.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/549,915
• Time in Patent Office: 736 Days
• Field of Search: 331/1 A, 331/2, 331/16, 331/17, 331/18, 331/25, 331/74, 331/108 D, 331/108 C, 337/105, 337/107, 337/147-150, 337/156-159, 455/260
• US Class Current: 331/16
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.

Claims

1. A circuit for generating a clock frequency comprising:

a configuration table having a set of outputs for storing a set of configuration information to determine said clock frequency;

an erasable and programmable non-volatile memory for storing said configuration table; and

a clock generator having a set of inputs coupled to said set of outputs of said configuration table, said clock generator for generating said clock frequency,

wherein said configuration table, said non-volatile memory and said clock generator are provided on a single chip.

2. The circuit according to claim 1 wherein said clock generator is comprised of a phase-locked-loop.

3. The circuit according to claim 1 wherein said configuration table is comprised of a frequency table for storing a set of frequency based configuration information for determining the frequency at which the clock output will oscillate and a general table for storing information that controls general information for the circuit.

4. The circuit according to claim 1 wherein said programmable non-volatile memory is comprised of an EPROM.

5. The circuit according to claim 1 wherein said programmable non-volatile memory is comprised of a single-poly EPROM.

6. The circuit according to claim 1 wherein said programmable non-volatile memory is programmable after said circuit is packaged.

7. The circuit according to claim 1 wherein said non-volatile memory can be programmed during a wafer sort step of the production process.

8. The circuit according to claim 1 wherein said non-volatile memory can be programmed in the field by the end user of the circuit.

9. A single chip circuit for generating a set of clock frequencies comprising:

a configuration table having a set of outputs for storing a set of configuration information to determine the frequencies at which a set of clock outputs oscillate;

an erasable and programmable non-volatile memory for storing said configuration table;

an internal or external reference frequency source that generates a reference output;

a first clock generator having a set of inputs coupled to said set of outputs of said configuration table and a reference input coupled to said reference output, said clock generator for generating one of said set of clock outputs at one of said frequencies determined by said configuration table;

a plurality of fixed frequency clock generators each having a set of inputs coupled to said configuration table and a reference input coupled to said reference output, each of said plurality of clock generators having an output signal that oscillates at a fixed frequency; and

a multiplexer having (i) a plurality of inputs connected to each of the outputs from said first clock generator and said plurality of clock generators and (ii) a bus input connected to one of said set of outputs of said configuration table, said multiplexer for presenting at least one of said clock output signals.

10. The circuit according to claim 9 wherein said clock generator and said plurality of clock generators are each comprised of a phase-locked-loop.

11. The circuit according to claim 9 wherein said configuration table is comprised of a frequency table for storing a set of frequency based configuration information for determining the frequency at which the fixed frequency clock will oscillate and a general table for storing information that controls general information for the circuit.

12. The circuit according to claim 9 wherein said multiplexer produces said single output signal in response to said bus input.

13. The circuit according to claim 9 wherein said configuration table has a select input connected to a plurality of external input selects, said select input provides external programming for producing a signal on said bus input of said multiplexer for determining which of said plurality of inputs will be produced at said set of output signals.

14. The circuit according to claim 11 wherein said general table has a select input connected to a plurality of external input selects, said select input provides external programming for producing a signal on said bus input of said multiplexer for determining which of said plurality of inputs will be produced at said set of output signals.

15. The circuit according to claim 9 wherein said programmable non-volatile memory is comprised of an EPROM.

16. The circuit according to claim 9 wherein said programmable non-volatile memory is comprised of a single-poly EPROM.

17. The circuit according to claim 9 wherein said programmable non-volatile memory is programmable after said circuit is packaged.

18. The circuit according to claim 9 wherein said non-volatile memory can be programmed during a wafer sort step of the production process.