Apparatus and method for improving the efficiency and quality of functional verification
First Claim
Patent Images
1. A design verification system comprising:
- test stimulus generator means for generating a plurality of input test stimuli for application to a device under test;
application means for applying said test stimuli to said device under test;
monitoring means for monitoring and recording responses of said device under test to said test stimuli and for monitoring occurrences of predetermined events resulting from said test stimuli;
correlation means coupled to said monitoring means and said test stimulus generator means for analyzing said responses to determine cause and effect relationships between input parameters of said test stimulus generation means and said responses and for providing modified input parameters to said test stimulus generator means in order for said test stimulus generator means to generate, in a controlled fashion, a second different plurality of test stimuli for producing desired responses and occurrences of said predetermined events.
4 Assignments
0 Petitions
Accused Products
Abstract
A design verification system is provided which includes the ability to automatically correlate the response of a device under test to the input stimuli. The test system uses a pseudo-random exerciser to produce a set of test stimuli for application to a device under test. Once applied, the response of the device is recorded and an automatic correlation is performed using a chosen correlation engine. Once the correlation is complete a new set of stimuli is produced which results in improved test coverage for the device under test. The system is closed-loop and thus allows for iterative testing of a device under test.
39 Citations
8 Claims
-
1. A design verification system comprising:
-
test stimulus generator means for generating a plurality of input test stimuli for application to a device under test; application means for applying said test stimuli to said device under test; monitoring means for monitoring and recording responses of said device under test to said test stimuli and for monitoring occurrences of predetermined events resulting from said test stimuli; correlation means coupled to said monitoring means and said test stimulus generator means for analyzing said responses to determine cause and effect relationships between input parameters of said test stimulus generation means and said responses and for providing modified input parameters to said test stimulus generator means in order for said test stimulus generator means to generate, in a controlled fashion, a second different plurality of test stimuli for producing desired responses and occurrences of said predetermined events. - View Dependent Claims (2, 3, 4)
-
-
5. A method of verifying a circuit design comprising the steps of:
-
a) generating, according to a set of parameters, a first set of test stimuli; b) applying said first set of test stimuli to a device under test; c) monitoring and recording responses of said device under test to said applied stimuli; d) correlating said responses with said applied stimuli to determine which input stimuli provide desired responses; e) modifying, based on said correlating step, said set of parameters associated with said generating step to provide parameters that produce said desired responses; f) generating, responsive to said modified set of parameters, a second set of test stimuli for providing increased test coverage; and g) repeating steps b through f until complete test coverage of said device under test is achieved and all desired responses have been produced. - View Dependent Claims (6, 7, 8)
-
Specification