Performance evaluation method and device thereof for a parallel computer

• US 5,684,947 A
• Filed: 06/01/1995
• Issued: 11/04/1997
• Est. Priority Date: 12/26/1991
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Horie, Takeshi
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Palys, Joseph E.
• Application Number:
  US08/456,615
• Time in Patent Office: 887 Days
• Field of Search: 395/183.21, 395/183.13, 395/183.14, 395/183.15, 395/183.22, 395/183.09, 395/185.08, 395/185.04
• US Class Current: 714/37
• CPC Class Codes: G06F 11/3419 by assessing time
• CPC Class Codes: G06F 11/3495 for systems

Abstract

A performance evaluation for a parallel computer which carries out parallel processing in multiple processor by means of transmitting or receiving a message among the processors. Execution starting time, standby starting time for waiting reception of the message, message number on reception of the message, processor number of the processor, the message and time when the message is received, message number on transmitting of the message and time when the message execution ending time are memorized. A maximum delay path is determined for the execution which has lastly been ended, the standby starting time for waiting reception of the message in the last ending processor, the message number of the last ending processor, the transmitting processor number and the message transmitting processor corresponding to the transmitting processor number. Processing is repeatedly carried out from the last ending processor to starting processor where execution of the parallel processing is started. Thus, the maximum delay path is identified.

Claims

1. A performance evaluation method for a parallel computer for carrying out parallel processing in each processor by transmitting or receiving a message among a plurality of processors, comprising the steps of:

memorizing step for memorizing various pieces of information in each processor in the parallel processing, said step includes memorizing the steps of;

(1) a step for memorizing execution starting time of the parallel processing;

(2) a step for memorizing a standby starting time for reception of the message when a standby starting time has been identified;

(3) a step for memorizing a message number on reception of said message, transmitting processor number and the time thereat;

(4) a step for memorizing a message number on transmitting the message, and the time thereat; and

(5) a step for memorizing execution ending time; and

maximum delay path obtaining step for obtaining, after execution of said parallel processing is completed, a maximum delay path showing a longest message transmitting route in accordance with the various pieces of information;

said maximum delay path obtaining step includes the steps of;

(a) a step for identifying the last ending processor in which the execution has lastly been completed in accordance with each time obtained in said step for memorizing execution ending time in each processor;

(b) a step for identifying the standby starting time for reception of the message obtained in said step (2) in an identified processor to obtain a waiting time interval;

(c) a step for identifying the message number and the transmitting processor number obtained in step (3) in the identified processor to obtain the longest message transmitting route; and

(d) a step for identifying a message transmitting processor corresponding to the transmitting processor number to obtain the longest message transmitting route;

said steps (b) through (d) are repeated regarding each processor from the last ending processor to starting processor where execution of the parallel processing is started, to obtain said maximum delay path.

2. A performance evaluation method for a parallel computer according to claim 1, wherein said maximum delay path obtaining step obtains the waiting time interval for a message in accordance with the time obtained in said step (b) and the time obtained in said step (c).

3. A performance evaluation method for a parallel computer according to claim 1, wherein in the case where processing carried out by the processors is interrupted until said all of the processors issue a barrier synchronous signal with a synchronous number on execution of said parallel processing,

said memorizing step further includes a step (6) for memorizing barrier synchronous number of said barrier synchronous signal and the time thereat:

said maximum delay path obtaining step further including a step (e) for identifying a processor which has lastly issued the barrier synchronous number and the time thereat obtained in said step (6) to obtain said maximum delay path.

4. A performance evaluation method for a parallel computer according to claim 3, wherein said maximum delay path obtaining step obtains a waiting time interval due to the barrier synchronous control in accordance with the time obtained in said step (e).

5. A performance evaluation method for a parallel computer according to claim 3, wherein said maximum delay path obtaining step further including a step (f) for displaying said obtained maximum delay path.

6. A performance evaluation method for a parallel computer according to claim 1, wherein said maximum delay path obtaining step further including a step (f) for displaying said obtained maximum delay path.

7. A performance evaluation method for a parallel computer according to claim 6, wherein said maximum delay path and message flow of the path are displayed with one axis on a display representing the time and the other axis thereon representing processors for displaying said maximum delay path.

8. A performance evaluation method for a parallel computer according to claim 6, wherein a waiting sate for said message is also displayed in said step (f) on displaying said maximum delay path.

9. A performance evaluation method for a parallel computer according to claim 6, wherein the number of said each processor being in operation is also displayed in said step (f) on displaying said maximum delay path.

10. A performance evaluation device for a parallel computer having a plurality of processors for executing parallel processing in each processor by transmitting a message from a starting processor and receiving and transmitting a message among a plurality of processors, comprising:

measuring means for measuring in each processor an execution starting time indicating when execution is started, a standby starting time for the reception of the message when a standby starting time has been identified, a receiving time indicating when the message was received, a transmitting time indicating when the message was transmitted, and an execution ending time indicating when execution stopped;

memorizing means for storing a message number of the message on reception of the message, a transmitting processor number that sent the message, a message number of the message on transmitting the message and each time measured by the measuring means;

comparing means for comparing the execution ending time of each processor;

searching means for identifying a last processor in which execution finished last based on the output of the comparing means, and for identifying a longest route of message transmission based on the message number corresponding to the standby starting time for each processor, the transmitting processor number corresponding to the standby starting time for each processor, and the message transmitting processor corresponding to the transmitting processor number in each processor; and

maximum delay path obtaining means for obtaining a maximum delay path indicating the longest route of the message transmission by repeatedly searching each processor from the last processor to the starting processor.

11. A performance evaluation device for a parallel computer according to claim 10, wherein said maximum delay path obtaining means comprises said comparing means and said searching means.

12. A performance evaluation device for a parallel computer according to claim 10, wherein said memorizing means, said comparing means and said searching means is provided in each of the plurality of processors, and wherein

comparison processing in said comparing means is carried out by said comparing means in parallel with the search processing in said searching means in each processor.

13. A performance evaluation device for a parallel computer according to claim 10, the device further comprising:

barrier synchronous control means for interrupting processing of the processor until all of the processors issue a barrier synchronous signal with a synchronous number for execution of said parallel processing,

said memorizing means further stores the synchronous number of said barrier synchronous signal and the time the signal is transmitted,

said comparing means compares said barrier synchronous numbers and the time the signal is transmitted with each other; and

said searching means obtains said maximum delay path by means of searching the processor which has lastly issued the barrier synchronous number.

14. A performance evaluation device for a parallel computer according to claim 10, wherein said maximum delay path obtaining means further comprises a displaying means for displaying said maximum delay path.

15. A performance evaluation device for a parallel computer according to claim 14, wherein said displaying means displays a maximum delay path and a message flow of the path wherein one axis on the display representing the time and the other axis represents processors.

16. A performance evaluation device for a parallel computer according to claim 14, wherein said displaying means also displays the waiting state for said message when displaying said maximum delay path.

17. A performance evaluation device for a parallel computer according to claim 14, wherein said displaying means also displays the number of each of said processors being used.

18. A performance evaluation method for a parallel computer having a plurality of processors for carrying out a parallel processing in each processor comprising;

originating a message from a starting processor;

transmitting the message among the plurality of 6 processors;

storing information in each processor regarding the parallel processing, including when a message was received by a particular processor, a standby starting time, and when the message was forwarded by the particular processor;

identifying the processor in which the message was last received based on the information stored in each processor; and

tracing a longest message transmitting route from the last processor to the starting processor by;

searching the standby starting time for reception of the message in the processor to obtain a waiting time interval;

searching a message number and a transmitting processor number in the processor to obtain the longest message transmitting route;

searching a message transmitting processor corresponding to the transmitting processor number to obtain the longest message transmitting route; and

repeating from the step for searching the standby starting time for each processor from the last processor to starting processor to obtain the maximum delay path.

19. A performance evaluation method, as set forth in claim 18, wherein the step of storing information in each processor comprises:

memorizing an execution starting time of the parallel processing;

memorizing a standby starting time for reception of the message;

memorizing a message number, a transmitting processor number and time the message was received on reception of the message;

memorizing a message number, and a time the message was transmitted on transmitting the message.

20. A performance evaluation method, as set forth in claim 19, wherein said identifying step comprises:

identifying the last processor in which the execution was completed in accordance with each time obtained in the step for memorizing execution ending time in each processor.

21. A performance evaluation method, as set forth in claim 18, wherein when processing carried out by the processor is interrupted until said all of the processors issue a barrier synchronous signal with a synchronous number on execution of said parallel processing, the step of storing information further comprises:

memorizing a barrier synchronous number from a barrier synchronous signal and the time when the signal was received; and

the step of tracing a longest message transmission route further includes searching a processor which has lastly issued the barrier synchronous number and the time received prior to the step of repeating.