FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions

• US 5,684,980 A
• Filed: 07/23/1996
• Issued: 11/04/1997
• Est. Priority Date: 07/29/1992
• Status: Expired due to Term

• Current Assignee: Tarofiss Data Limited Liability Company
• Original Assignee: Virtual Computer Incorporated (Cloud Software Group)
• Inventors: Casselman, Steven Mark
• Primary Examiner(s): Ellis, Richard L.
• Application Number:
  US08/685,158
• Time in Patent Office: 469 Days
• Field of Search: 395/800, 364/488, 364/489, 364/490, 364/491, 364/578, 340/825.83, 340/825.86, 340/825.87
• US Class Current: 703/23
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification

Abstract

An array of FPGAs change their configurations successively during performance of successive user-defined algorithms. Adjacent FPGAs are connected through external field programmable interconnection devices (FPINs) or cross-bar switches. The array includes a processor-like device capable of performing the computations necessary to reconfigure the FPGAs in the array in accordance with the next algorithm to be performed. Preferably, this processor-like device is itself a "control" array of interconnected FPGAs which have been configured to emulate a selected microprocessor architecture which accepts user-defined primitives corresponding to an algorithm to be performed or a logic architecture to be emulated and reconfigure the FPGAs and the FPINs accordingly.

Claims

1. A computer, comprising:

a plurality of field programmable gate arrays (FPGAs);

a plurality of control field programmable gate arrays (control FPGAs), comprising;

(a) a first group of gates comprising means for generating from each one of a succession of computing operations, corresponding to a succession of instructions defining a program to be executed, a plurality of logic configurations defining (a) an internal logic structure of a corresponding one of said FPGAs and (b) external connections between said corresponding FPGA and others of said FPGAs, whereby to generate a succession of logic configurations for each one of said FPGAs corresponding to said succession of predetermined computing operations; and

(b) a second group of gates comprising means for configuring each one of said FPGAs in accordance with a corresponding succession of logic configurations, whereby said plurality of FPGAs is successively reconfigured to perform said succession of predetermined computing operations sequentially so as to execute said sequence of instructions.

2. The computer of claim 1 wherein said array of control FPGAs is configured to function as a processor, said computer further comprising a memory connected to said array of control FPGAs and storing a user program containing instructions defining said succession of computing operations, whereby said array of control FPGAs fetches sequential ones of said instructions from said memory for execution in said plurality of FPGAs.

3. The computer of claim 1 wherein said means for configuring comprises means for controlling (a) the internal logic structure of each FPGA and (b) the external connections between each FGPA and others of said FPGAs.

4. The computer of claim 3 wherein:

said means for controlling comprises means for generating a configuration bit file defining said internal logic structure and said external connections and transmitting at least a portion of said configuration bit file corresponding to said internal logic structure to the corresponding FPGA; and

each one of said FPGAs comprises means responsive to receipt of a configuration bit file for conforming internal logic resources of said one FGPA in accordance with said internal logic structure defined by said configuration bit file.

5. The computer of claim 4 wherein said first group of gates is configured to process an input file defining a predetermined computing operation so as to produce a plurality of configuration bit files corresponding to said plurality of FPGAs.

6. The computer of claim 5 further comprising conductor means for providing a configuration bit data path between said array of control FPGAs and said plurality of FPGAs for said configuration bit files.

7. The computer of claim 5 wherein said array of control FPGAs is configured to emulate architecture of a microprocessor capable of executing an object code which generates said configuration bit files from said input file.

8. The computer of claim 6 wherein said conductor means provides parallel bit-serial data paths for each of said configuration files to a respective one of said plurality of FPGAs, whereby said plurality of FPGAs are reconfigurable simultaneously.

9. The computer of claim 6 further comprising a plurality of field programmable interconnect devices (FPINs), each of said FPINs comprising means for providing reconfigurable connections among respective sets of said plurality of FPGAs in conformance with said external connections defined by respective ones of said configuration bit files.

10. The computer of claim 9 wherein:

said means for controlling further comprises means for transmitting a portion of said configuration bit file corresponding to said external connections to a corresponding FPIN; and

each one of said FPINs comprises means responsive to receipt of a configuration bit file for conforming internal connection resources of said one FPIN in accordance with said external connections defined by said configuration bit file.

11. The computer of claim 9 wherein each of said FPINs comprises a plurality of external connections and an array of general routing cells (GRCs), each of said GRCs comprising:

a programmable switch for connecting a corresponding pair of said external connections in response to a configuration bit of a configuration bit file; and

means for controlling said programmable switch in accordance with a corresponding bit of a first configuration bit file while propagating the bits of a second configuration bit file through said array of GRCs along one of said pair of external connections.

12. The computer of claim 11 wherein said array of GRCs is a serpentine array whereby said bits of said second configuration bit file propagate serially in a serpentine path extending through all of said GRCs.

13. The computer of claim 9 wherein said plurality of FPGAs and said plurality of FPINs are arranged in an array of identical building blocks, each building block comprising a pair of FPGAs and a pair of FPINs, each FPGA of said building block being connected to the pair of FPINs of said building block and to two FPINs of adjacent building blocks in said array, and each FPIN of said building block being connected to the pair of FPGAs of said building block and to two FPGAs of adjacent building blocks.

14. The computer of claim 13 further comprising FPGA column buses connected to FPGAs within the same column of said array and FPIN row buses connected to FPINs in the same row of said array.

15. The computer of claim 14 wherein each FPGA comprises five banks of separate external connections to its internal logic resources and wherein each FPIN comprises five banks of separate external connections to its internal connection resources, and wherein four of said five banks of each FPGA connect to four FPINs and the remaining bank connects to an FPGA column bus, while four of said five banks of each FPIN connect to four FPGAs and the remaining bank connects to an FPIN row bus.

16. The computer of claim 15 wherein each of said FPGAs and FPINs has a configuration bit input pin connected by said configuration data path to a configuration bit output pin of one of said control FPGAs.

17. The computer of claim 16 further comprising means for providing a operation data path between said array of control FPGAs and said array of FPGAs and FPINs comprising means for buffering operation data flowing between said control FPGAs and said array of FPGAs and FPINs.

18. The computer of claim 16 further comprising means for connecting each FPGA at an edge of said array of FPGAs and FPINs to an FPGA at an opposite edge thereof in the same row or column and for connecting each FPIN at an edge of said array of FPGAs and FPINs to an FPIN at an opposite edge thereof in the same row or column.

19. A method of operating an array of plural field programmable gates (FPGs) and a controller in order to execute a program defined by a sequence of instructions, comprising:

said controller fetching information defining a succession of computing operations, each of said computing operations corresponding to a respective group of at least a respective one of said sequence of instructions;

said controller generating from said succession of computing operations a corresponding succession of sets of respective plural logic configurations for reinactive ones of said plural FPGs, each of said logic configurations within a set defining (a) an internal logic structure of a corresponding one of said FPGs and (b) external connections between said corresponding FPG and others of said FPGs, whereby to generate a succession of logic configurations for each one of said FPGs corresponding to said succession of computing operations;

said controller configuring each one of said array of FPGs in accordance with a corresponding succession of logic configurations, wherein said array of FPGs is successively reconfigured to perform said succession of computing operations sequentially so as to execute said sequence of instructions of said program.

20. The method of claim 19 wherein said configuring comprises controlling (a) the internal logic structure of each FPG and (b) the external connections between each FPG and others of said FPGs in said array of FPGs.

21. The method of claim 20 wherein:

controlling comprises generating a configuration bit file defining said internal logic structure and said external connections and transmitting at least a portion of said configuration bit file corresponding to said internal logic structure to the corresponding FPG.

22. The method of claim 21 wherein:

said array of FPGs are interconnectable through a plurality of field programmable interconnect devices (FPINs), each of said FPINs providing reconfigurable connections among respective sets of FPGs in said array of FPGs in response to receipt of a corresponding configuration bit file; and

said controlling further comprises transmitting a portion of said configuration bit file corresponding to said external connections to a corresponding FPIN.

23. A computer, comprising:

a plurality of field programmable gates (FPGs);

a plurality of control field programmable gates (control FPGs), comprising;

(a) a first group of gates comprising means for generating from each one of a succession of predetermined computing operations a plurality of logic configurations corresponding to said plurality of FPGs, each of said logic configurations defining (a) an internal logic structure of a corresponding one of said FPGs and (b) external connections between said corresponding FPG and others of said FPGs, whereby to generate a succession of logic configurations for each one of said FPGs corresponding to said succession of predetermined computing operations; and

(b) a second group of gates comprising means for configuring each one of said FPGs in accordance with a corresponding succession of logic configurations, whereby said plurality of FPGs is successively reconfigured to perform said succession of predetermined computing operations sequentially.

24. The computer of claim 23 wherein said plurality of control FPGs is configured to function as a processor, said computer further comprising a memory connected to said plurality of control FPGs and storing a user program containing instructions defining said succession of computing operations, and said first group of gates of said control FPGs fetches sequential ones of said instructions from said memory for execution in said plurality of FPGs.

25. The computer of claim 23 wherein said means for configuring comprises means for controlling (a) the internal logic structure of each FPG and (b) the external connections between each FGP and others of said FPGs.

26. The computer of claim 25 wherein:

said means for controlling comprises means for generating a configuration bit file defining said internal logic structure and said external connections and transmitting at least a portion of said configuration bit file corresponding to said internal logic structure to the corresponding FPG; and

each one of said FPGs comprises means responsive to receipt of a configuration bit file for conforming internal logic resources of said one FGP in accordance with said internal logic structure defined by said configuration bit file.

27. The computer of claim 26 wherein said first group of gates is configured to process an input file defining a predetermined computing operation so as to produce a plurality of configuration bit files corresponding to said plurality of FPGs.

28. The computer of claim 27 wherein said plurality of control FPGs is configured to emulate architecture of a microprocessor capable of executing an object code which generates said configuration bit files from said input file.

29. The computer of claim 27 further comprising conductor means for providing a configuration bit data path between said plurality of control FPGs and said plurality of FPGs for said configuration bit files.

30. The computer of claim 29 wherein said conductor means provides parallel bit-serial data paths for each of said configuration files to a respective one of said plurality of FPGs, whereby said plurality of FPGs are reconfigurable simultaneously.

31. The computer of claim 29 further comprising a plurality of field programmable interconnect devices (FPINs), each of said FPINs comprising means for providing reconfigurable connections among respective sets of said plurality of FPGs in conformance with said external connections defined by respective ones of said configuration bit files.

32. The computer of claim 31 wherein:

said means for controlling further comprises means for transmitting a portion of said configuration bit file corresponding to said external connections to a corresponding FPIN; and

each one of said FPINs comprises means responsive to receipt of a configuration bit file for conforming internal connection resources of said one FPIN in accordance with said external connections defined by said configuration bit file.

33. A method of operating an array of field programmable gates (FPGs) connected to an array of control field programmable gates, comprising:

said array of control FPGs fetching information defining a succession of predetermined computing operations;

generating in said control FPGs from each one of said succession of predetermined computing operations a plurality of logic configurations corresponding to said array of FPGs, each of said logic configurations defining (a) an internal logic structure of a corresponding one of said FPGs and (b) external connections between said corresponding FPG and others of said FPGs, whereby to generate a succession of logic configurations for each one of said FPGs corresponding to said succession of predetermined computing operations;

said array of control FPGs configuring each one of said array of FPGs in accordance with a corresponding succession of logic configurations, wherein said array of FPGs is successively reconfigured to perform said succession of predetermined computing operations sequentially.

34. The method of claim 33 wherein said configuring comprises controlling (a) the internal logic structure of each FPG and (b) the external connections between each FPG and others of said FPGs in said array of FPGs.

35. The method of claim 34 wherein:

said controlling comprises generating a configuration bit file defining said internal logic structure and said external connections and transmitting at least a portion of said configuration bit file corresponding to said internal logic structure to the corresponding FPG.

36. The method of claim 35 wherein:

said array of FPGs are interconnectable through a plurality of field programmable interconnect devices (FPINs), each of said FPINs providing reconfigurable connections among respective sets of FPGs in said array of FPGs in response to receipt of a corresponding configuration bit file; and

said controlling further comprises transmitting a portion of said configuration bit file corresponding to said external connections to a corresponding FPIN.