Multi-segmented bus and method of operation

• US 5,685,004 A
• Filed: 03/01/1993
• Issued: 11/04/1997
• Est. Priority Date: 03/06/1990
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Bruce, Richard H., Gastinel, Jean, Gunning, William F., Overton, Michael
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): HARRITY, JOHN E
• Application Number:
  US08/024,877
• Time in Patent Office: 1,709 Days
• Field of Search: 395/800, 395/775, 395/375, 395/325, 395/250, 371/22.3
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438

Abstract

A multi-level hierarchical bus architecture implemented with a multi-chip package and a modular shared-bus provides high bandwidth. All IC components are mounted on standardized multi-chip packages. Each multi-chip package includes bus interface chips for providing communication from the integrated circuits to a board bus. One multi-chip package contains additional bus interface circuitry for providing communication from the board bus to a backplane bus.

Claims

1. In a computing system having a plurality of data sources and receivers, a synchronous segmented bus for use in data transmission among said sources and receivers, said synchronous segmented bus comprising:

a plurality of bus segments for conveying multi-bit data in parallel, each segment having two ends, at least one bus segment being coupled to each source and receiver;

a plurality of registers including at least first, second, and third registers, said plurality of registers providing coupling between said bus segments, and being connected to said bus segments such that

each end of each of said bus segments which is not coupled to a source or receiver is connected to one of said plurality of registers,

said registers for receiving multi-bit data from a connected bus segment and for sending multi-bit data onto a connected bus segment,

said first register is coupled to one end of a first bus segment,

said second register is coupled to the other end of said first bus segment and to one end of a second bus segment without said second bus segment being coupled to said first register, and

said third register is coupled to the other end of said second bus segment; and

means for clocking said first, second, and third registers such that said registers latch and send data synchronously under the control of a common clock signal, wherein

multi-bit data sent from said first register travels on said first bus segment and is received at said second register in a first clock cycle,

said multi-bit data received at said second register is sent from said second register, travels on said second bus segment, and is received at said third register in a second clock cycle without said multi-bit data being sent over said first bus segment during said second clock cycle,

multi-bit data received in said third register is identical to said multi-bit data sent from said first register and identical to said multi-bit data sent from said second register, and

the duration of each clock cycle is equal to the sum of a segment overhead time and the maximum of the respective times required for a signal to propagate from one end of a respective one of the bus segments to the other end of the respective bus segment.

2. A synchronous segmented bus, as claimed in claim 1, wherein said computing system includes a plurality of processors.

3. A synchronous segmented bus for use in data transmission, said synchronous segmented bus comprising:

at least first and second bus segments for conveying multi-bit data in parallel, each segment having two ends;

at least first, second, and third registers for receiving multi-bit data from a connected bus segment and for sending multi-bit data onto a connected bus segment, said first register being coupled to one end of said first bus segment, said second register being coupled to the other end of said first bus segment and to one end of said second bus segment without said second bus segment being coupled to said first register, said third register being coupled to the other end of said second bus segment; and

means for clocking said first, second, and third registers, wherein

said registers latch and send data synchronously under the control of a common clock signal,

first multi-bit data sent from said first register is received at said second register in one clock cycle, synchronously with sending second multi-bit data from said second register to said third register,

said first multi-bit data is sent from said second register and received at said third register in a second clock cycle, without said first multi-bit data being sent over said first bus segment during said second clock cycle and

the duration of each clock cycle is equal to the sum of a segment overhead time and the maximum of the respective times required for a signal to propagate from one end of a respective one of the bus segments to the other end of the respective bus segment.

4. A synchronous segmented bus for use in data transmission, said synchronous segmented bus comprising:

a plurality of bus segments for conveying multi-bit data in parallel, each segment having two ends;

a plurality of registers including at least first, second, and third registers, said plurality of registers providing coupling between said bus segments, and being connected to said bus segments such that

each end of each of said bus segments is connected to one of said plurality of registers,

each of said plurality of registers receives multi-bit data from a connected bus segment and sends multi-bit data onto a connected bus segment,

said first register is coupled to one end of a first bus segment,

said second register is coupled to the other end of said first bus segment and to one end of a second bus segment without said second bus segment being coupled to said first register, and

said third register is coupled to the other end of said second bus segment; and

means for clocking said first, second, and third registers such that said registers latch and send data synchronously under the control of a common clock signal, wherein

multi-bit data sent from said first register travels on said first bus segment and is received at said second register in a first cycle,

said multi-bit data received at said second register is sent from said second register, travels on said second bus segment, and is received at said third register in a second clock cycle, without said multi-bit data being sent over said first bus segment during said second clock cycle,

said multi-bit data received in said third register is identical to said multi-bit data sent from said first register and identical to said multi-bit data sent from said second register, and

said first bus segment is a backplane bus and said second bus segment is a board bus.

5. A synchronous segmented bus for use in data transmission, said synchronous segmented bus comprising:

a plurality of bus segments for conveying multi-bit data in parallel, each segment having two ends;

a plurality of registers including at least first, second, and third registers, said plurality of registers providing coupling between said bus segments, and being connected to said bus segments such that

each end of each of said bus segments is connected to one of said plurality of registers,

each of said plurality of registers receives multi-bit data from a connected bus segment and sends multi-bit data onto a connected bus segment,

said first register is coupled to one end of a first bus segment,

said second register is coupled to the other end of said first bus segment and to one end of a second bus segment without said second bus segment being coupled to said first register, and

said third register is coupled to the other end of said second bus segment; and

means for clocking said first, second, and third registers such that said registers latch and send data synchronously under the control of a common clock signal, wherein

multi-bit data sent from said first register travels on said first bus segment and is received at said second register in a first cycle,

said multi-bit data received at said second register is sent from said second register, travels on said second bus segment, and is received at said third register in a second clock cycle, without said multi-bit data being sent over said first bus segment during said second clock cycle,

said multi-bit data received in said third register is identical to said multi-bit data sent from said first register and identical to said multi-bit data sent from said second register, and

at least one of said bus segments includes a first unidirectional portion for transmitting data in a first direction and a second unidirectional portion for transmitting data in a second direction simultaneously with said transmitting of data in said first direction, said second direction being different from said first direction.

6. A synchronous segmented bus for use in data transmission, said synchronous segmented bus comprising:

a plurality of bus segments for conveying multi-bit data in parallel, each segment having two ends;

a plurality of registers including at least first, second, and third registers, said plurality of registers providing coupling between said bus segments, and being connected to said bus segments such that

each end of each of said bus segments is connected to one of said plurality of registers,

each of said plurality of registers receives multi-bit data from a connected bus segment and sends multi-bit data onto a connected bus segment,

said first register is coupled to one end of a first bus segment,

said second register is coupled to the other end of said first bus segment and to one end of a second bus segment without said second bus segment being coupled to said first register, and

said third register is coupled to the other end of said second bus segment; and

means for clocking said first, second, and third registers such that said registers latch and send data synchronously under the control of a common clock signal, wherein

multi-bit data sent from said first register travels on said first bus segment and is received at said second register in a first cycle,

said multi-bit data received at said second register is sent from said second register, travels on said second bus segment, and is received at said third register in a second clock cycle, without said multi-bit data being sent over said first bus segment during said second clock cycle,

said multi-bit data received in said third register is identical to said multi-bit data sent from said first register and identical to said multi-bit data sent from said second register, and

one of said bus segments is bi-directional and all other bus segments include a first unidirectional portion for transmitting data in a first direction and a second unidirectional portion for transmitting data in a second direction simultaneously with said transmitting of data in said first direction, said second direction being different from said first direction.

7. A synchronous segmented bus, as claimed in claim 6, wherein said bi-directional bus segment is a backplane bus.

8. A synchronous segmented shared bus for communication in a computer, said synchronous segmented shared bus comprising:

a plurality of bus segments for conveying multi-bit data in parallel including at least one lowest-level bus segment and one highest-level bus segment, each of said plurality of bus segments being connected for communication with at least one other bus segment, said plurality of bus segments connected to define a plurality of ordered bus levels wherein each bus segment can communicate with at least one other bus segment which is in an adjacent level; and

a plurality of registers including at least first, second, and third registers, said plurality of registers connected to said plurality of bus segments for holding multi-bit data received from a bus segment before said multi-bit data is sent to an adjacent-level bus segment, said first register being coupled to one end of a first bus segment, said second register being coupled to the other end of said first bus segment and to one end of a second bus segment without said second bus segment being connected to said first register, said third register being coupled to the other end of said second bus segment, wherein

when said multi-bit data is sent from one of said registers, over a bus segment to a second of said registers, said multi-bit data is unchanged;

said registers latch and send data synchronously under the control of a common clock signal; and

at least two of the bus segments have differing electrical characteristics.

9. The synchronous segmented shared bus of claim 8 wherein signals on said bus segments have a voltage level and wherein the voltage level of signals corresponding to a logic level on at least one bus segment is different from the voltage level of signals corresponding to the logic level on an adjacent-level bus segment.

10. A synchronous segmented bus for use in data transmission, said synchronous segmented bus comprising:

a plurality of bus segments for conveying multi-bit data in parallel, each segment having two ends;

a plurality of registers including at least first, second, and third registers, said plurality of registers providing coupling between said bus segments, and being connected to said bus segments such that

each end of each of said bus segments is connected to one of said plurality of registers,

each of said plurality of registers receives multi-bit data from a connected bus segment and sends multi-bit data onto a connected bus segment,

said first register is coupled to one end of a first bus segment,

said second register is coupled to the other end of said first bus segment and to one end of a second bus segment without said second bus segment being coupled to said first register, and

said third register is coupled to the other end of said second bus segment; and

means for clocking said first, second, and third registers such that said registers latch and send data synchronously under the control of a common clock signal, wherein

multi-bit data sent from said first register travels on said first bus segment and is received at said second register in a first cycle,

said multi-bit data received at said second register is sent from said second register, travels on said second bus segment, and is received at said third register in a second clock cycle, without said multi-bit data being sent over said first bus segment during said second clock cycle,

said multi-bit data received in said third register is identical to said multi-bit data sent from said first register and identical to said multi-bit data sent from said second register, and

said first bus segment is a backplane bus.

11. A synchronous segmented bus for use in data transmission, said synchronous segmented bus comprising:

a plurality of bus segments for conveying multi-bit data in parallel, each segment having two ends;

a plurality of registers including at least first, second, and third registers, said plurality of registers providing coupling between said bus segments, and being connected to said bus segments such that

each end of each of said bus segments is connected to one of said plurality of registers,

each of said plurality of registers receives multi-bit data from a connected bus segment and sends multi-bit data onto a connected bus segment,

said first register is coupled to one end of a first bus segment,

said second register is coupled to the other end of said first bus segment and to one end of a second bus segment without said second bus segment being coupled to said first register, and

said third register is coupled to the other end of said second bus segment; and

means for clocking said first, second, and third registers such that said registers latch and send data synchronously under the control of a common clock signal, wherein

multi-bit data sent from said first register travels on said first bus segment and is received at said second register in a first cycle,

said multi-bit data received at said second register is sent from said second register, travels on said second bus segment, and is received at said third register in a second clock cycle, without said multi-bit data being sent over said first bus segment during said second clock cycle,

said multi-bit data received in said third register is identical to said multi-bit data sent from said first register and identical to said multi-bit data sent from said second register, and

said first bus segment is a backplane bus and said second bus segment is a multi-chip carrier bus.

12. A synchronous segmented bus for use in data transmission, said synchronous segmented bus comprising:

a plurality of bus segments for conveying multi-bit data in parallel, each segment having two ends;

a plurality of registers including at least first, second, and third registers, said plurality of registers providing coupling between said bus segments, and being connected to said bus segments such that

each end of each of said bus segments is connected to one of said plurality of registers,

each of said plurality of registers receives multi-bit data from a connected bus segment and sends multi-bit data onto a connected bus segment,

said first register is coupled to one end of a first bus segment,

said second register is coupled to the other end of said first bus segment and to one end of a second bus segment without said second bus segment being coupled to said first register, and

said third register is coupled to the other end of said second bus segment; and

means for clocking said first, second, and third registers such that said registers latch and send data synchronously under the control of a common clock signal, wherein

multi-bit data sent from said first register travels on said first bus segment and is received at said second register in a first cycle,

said multi-bit data received at said second register is sent from said second register, travels on said second bus segment, and is received at said third register in a second clock cycle, without said multi-bit data being sent over said first bus segment during said second clock cycle,

said multi-bit data received in said third register is identical to said multi-bit data sent from said first register and identical to said multi-bit data sent from said second register, and

said first bus segment is a board bus and said second bus segment is a multi-chip carrier bus.