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Multi-segmented bus and method of operation

  • US 5,685,004 A
  • Filed: 03/01/1993
  • Issued: 11/04/1997
  • Est. Priority Date: 03/06/1990
  • Status: Expired due to Term
First Claim
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1. In a computing system having a plurality of data sources and receivers, a synchronous segmented bus for use in data transmission among said sources and receivers, said synchronous segmented bus comprising:

  • a plurality of bus segments for conveying multi-bit data in parallel, each segment having two ends, at least one bus segment being coupled to each source and receiver;

    a plurality of registers including at least first, second, and third registers, said plurality of registers providing coupling between said bus segments, and being connected to said bus segments such thateach end of each of said bus segments which is not coupled to a source or receiver is connected to one of said plurality of registers,said registers for receiving multi-bit data from a connected bus segment and for sending multi-bit data onto a connected bus segment,said first register is coupled to one end of a first bus segment,said second register is coupled to the other end of said first bus segment and to one end of a second bus segment without said second bus segment being coupled to said first register, andsaid third register is coupled to the other end of said second bus segment; and

    means for clocking said first, second, and third registers such that said registers latch and send data synchronously under the control of a common clock signal, whereinmulti-bit data sent from said first register travels on said first bus segment and is received at said second register in a first clock cycle,said multi-bit data received at said second register is sent from said second register, travels on said second bus segment, and is received at said third register in a second clock cycle without said multi-bit data being sent over said first bus segment during said second clock cycle,multi-bit data received in said third register is identical to said multi-bit data sent from said first register and identical to said multi-bit data sent from said second register, andthe duration of each clock cycle is equal to the sum of a segment overhead time and the maximum of the respective times required for a signal to propagate from one end of a respective one of the bus segments to the other end of the respective bus segment.

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