Method for forming a metal oxide semiconductor field effect transistor (MOSFET) having improved hot carrier immunity
First Claim
1. A method for fabricating a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) comprising:
- forming upon a semiconductor substrate a gate dielectric layer, the gate dielectric layer having a gate electrode formed thereupon, the gate dielectric layer extending beyond a pair of opposite edges of the gate electrode, the gate electrode layer being formed at least in part from a first doped polysilicon layer;
forming into the semiconductor substrate directly adjoining the pair of opposite edges of the gate electrode a pair of low dose ion implants;
forming upon the gate dielectric layer and contacting the pair of opposite edges of the gate electrode a pair of conductive spacers, the pair of conductive spacers partially overlapping the pair of low dose ion implants, the pair of conductive spacers being formed from a second doped polysilicon layer; and
forming into the semiconductor substrate adjoining the pair of opposite edges of the gate electrode and further removed from the pair of conductive spacers a pair of source/drain electrodes, the pair of source/drain electrodes partially overlapping the pair of low dose ion implants, where at least either;
the first doped polysilicon layer is employed in forming over the semiconductor substrate, simultaneously with the gate electrode, a first polysilicon capacitor electrode within a double layer polysilicon capacitor;
orthe second doped polysilicon layer is employed in forming over the semiconductor substrate, simultaneously with the pair of conductive spacers, a second polysilicon capacitor electrode within the double layer polysilicon capacitor.
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Accused Products
Abstract
A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) exhibiting enhanced immunity to Hot Carrier Effects (HCEs), and a method by which the MOSFET may be formed. To form the MOSFET there is first provided a semiconductor substrate having a gate dielectric layer formed thereupon. The gate dielectric layer has a gate electrode formed thereupon, where the gate dielectric layer extends beyond a pair of opposite edges of the gate electrode. Formed into the semiconductor substrate adjoining the pair of opposite edges of the gate electrode is a pair of low dose ion implants. Formed upon the gate dielectric layer and contacting the pair of opposite edges of the gate electrode is a pair of conductive spacers. The pair of conductive spacers partially overlaps the pair of low dose ion implants. Finally, there is formed into the semiconductor substrate adjoining the pair of opposite edges of the gate electrode and further removed from the pair of conductive spacers a pair of source/drain electrodes. The pair of source/drain electrodes partially overlaps the pair of low dose ion implants. Optionally, a pair of insulator spacers may be formed upon the pair of conductive spacers to adjust the partial overlap of the pair of source/drain electrodes and the pair of low dose ion implants.
34 Citations
9 Claims
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1. A method for fabricating a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) comprising:
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forming upon a semiconductor substrate a gate dielectric layer, the gate dielectric layer having a gate electrode formed thereupon, the gate dielectric layer extending beyond a pair of opposite edges of the gate electrode, the gate electrode layer being formed at least in part from a first doped polysilicon layer; forming into the semiconductor substrate directly adjoining the pair of opposite edges of the gate electrode a pair of low dose ion implants; forming upon the gate dielectric layer and contacting the pair of opposite edges of the gate electrode a pair of conductive spacers, the pair of conductive spacers partially overlapping the pair of low dose ion implants, the pair of conductive spacers being formed from a second doped polysilicon layer; and forming into the semiconductor substrate adjoining the pair of opposite edges of the gate electrode and further removed from the pair of conductive spacers a pair of source/drain electrodes, the pair of source/drain electrodes partially overlapping the pair of low dose ion implants, where at least either; the first doped polysilicon layer is employed in forming over the semiconductor substrate, simultaneously with the gate electrode, a first polysilicon capacitor electrode within a double layer polysilicon capacitor;
orthe second doped polysilicon layer is employed in forming over the semiconductor substrate, simultaneously with the pair of conductive spacers, a second polysilicon capacitor electrode within the double layer polysilicon capacitor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification