Conductor reticulation for improved device planarity
First Claim
1. A method of constructing a planarized dielectric over a patterned conductor and adjacent regions on a semiconductor device, said method comprising:
- (a) depositing a layer of conducting material on a substrate;
(b) removing said layer of conducting material in a circumscribing region upon said substrate, thereby defining a location for and peripheral walls for said conductor;
(c) removing said layer of conducting material from at least one region within said circumscribing region to form internal and/or notch walls for said conductor, thereby dividing current-carrying capability for said conductor amongst at least two integrally-formed conducting segments of smaller minimum horizontal dimension than said conductor;
(d) depositing an insulating seed layer over said conductor and said substrate; and
(e) forming an insulating layer of silicon dioxide over said conductor and said substrate by a method of simultaneous CVD and back-sputtering.
1 Assignment
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Accused Products
Abstract
A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g., chemical mechanic polishing or etchback, may be reduced or avoided entirely.
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Citations
18 Claims
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1. A method of constructing a planarized dielectric over a patterned conductor and adjacent regions on a semiconductor device, said method comprising:
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(a) depositing a layer of conducting material on a substrate; (b) removing said layer of conducting material in a circumscribing region upon said substrate, thereby defining a location for and peripheral walls for said conductor; (c) removing said layer of conducting material from at least one region within said circumscribing region to form internal and/or notch walls for said conductor, thereby dividing current-carrying capability for said conductor amongst at least two integrally-formed conducting segments of smaller minimum horizontal dimension than said conductor; (d) depositing an insulating seed layer over said conductor and said substrate; and (e) forming an insulating layer of silicon dioxide over said conductor and said substrate by a method of simultaneous CVD and back-sputtering. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of forming a planarized insulated interconnection layer on a semiconductor device, said method comprising:
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(a) depositing a first layer of conducting material on a substrate; (b) removing sections of said first layer of conducting material in a first pattern, thereby forming a plurality of conducting regions, at least one of said conducting regions being a reticulated conductor, said reticulated conductor comprising a set of integrally-formed conducting segments which provide multiple conducting paths between opposing ends of said reticulated conductor; (c) depositing one or more insulating layers over said conducting regions and said substrate, at least one of said insulating layers deposited by a method of simultaneous deposition and back-sputtering; and (d) depositing and patterning a second layer of conducting material over a top surface of said insulating layers, whereby said top surface of a portion of said insulating layer in the immediate vicinity of said reticulated conductor have improved planarization as compared to a top surface of a similar insulating layer overlying a non-reticulated conductor of equivalent length and resistivity. - View Dependent Claims (8, 9, 10, 18)
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11. A method of constructing a planarized dielectric over a patterned conductor and adjacent regions on a semiconductor device, said method comprising:
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(a) depositing a first layer of conducting material on a substrate; (b) removing said first layer of conducting material in a circumscribing region upon said substrate, thereby defining a location for and peripheral walls for said conductor; (c) removing said first layer of conducting material from at least one region within said circumscribing region to form internal and/or notch walls for said conductor, thereby dividing current-carrying capability for said conductor amongst at least two integrally-formed conducting segments of smaller minimum horizontal dimension than said conductor; (d) forming an insulating layer over said conductor and said substrate by a deposition method which selectively planarizes features in order of smallest to largest based on minimum horizontal dimension; and (e) depositing and patterning a second layer of conducting material overlying said insulating layer. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification