Conductor reticulation for improved device planarity

• US 5,686,356 A
• Filed: 09/30/1994
• Issued: 11/11/1997
• Est. Priority Date: 09/30/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Jain, Manoj Kumar, Chisholm, Michael Francis
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Everhart, C.
• Application Number:
  US08/315,529
• Time in Patent Office: 1,138 Days
• Field of Search: 437/195, 437/228 POL, 437/228 PL, 437/245, 437/235
• US Class Current: 438/624
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g., chemical mechanic polishing or etchback, may be reduced or avoided entirely.

Claims

1. A method of constructing a planarized dielectric over a patterned conductor and adjacent regions on a semiconductor device, said method comprising:

(a) depositing a layer of conducting material on a substrate;

(b) removing said layer of conducting material in a circumscribing region upon said substrate, thereby defining a location for and peripheral walls for said conductor;

(c) removing said layer of conducting material from at least one region within said circumscribing region to form internal and/or notch walls for said conductor, thereby dividing current-carrying capability for said conductor amongst at least two integrally-formed conducting segments of smaller minimum horizontal dimension than said conductor;

(d) depositing an insulating seed layer over said conductor and said substrate; and

(e) forming an insulating layer of silicon dioxide over said conductor and said substrate by a method of simultaneous CVD and back-sputtering.

2. The method of claim 1, further comprising depositing and patterning a second layer of conducting material overlying said insulating layer.

3. The method of claim 1, further comprising depositing a CVD insulating layer over said conductor and said substrate, subsequent to forming step (d).

4. The method of claim 1, further comprising chemical-mechanical polishing said insulating layer.

5. The method of claim 1, wherein said conducting segments are formed to minimum design rule specifications for said semiconductor device.

6. The method of claim 1, wherein steps (b) and (c) are performed simultaneously.

7. A method of forming a planarized insulated interconnection layer on a semiconductor device, said method comprising:

(a) depositing a first layer of conducting material on a substrate;

(b) removing sections of said first layer of conducting material in a first pattern, thereby forming a plurality of conducting regions, at least one of said conducting regions being a reticulated conductor, said reticulated conductor comprising a set of integrally-formed conducting segments which provide multiple conducting paths between opposing ends of said reticulated conductor;

(c) depositing one or more insulating layers over said conducting regions and said substrate, at least one of said insulating layers deposited by a method of simultaneous deposition and back-sputtering; and

(d) depositing and patterning a second layer of conducting material over a top surface of said insulating layers, whereby said top surface of a portion of said insulating layer in the immediate vicinity of said reticulated conductor have improved planarization as compared to a top surface of a similar insulating layer overlying a non-reticulated conductor of equivalent length and resistivity.

8. The method of claim 7, further comprising, before step (d), chemical mechanical polishing said top surface of said insulating layers, whereby said insulating layer overlying said reticulated conductor has a higher polish rate as compared to the polish rate of the insulating layer overlying a non-reticulated conductor of equivalent length and resistivity.

9. The method of claim 7, wherein step (c) comprises depositing silicon dioxide by simultaneous CVD and back-sputtering.

10. The method of claim 9, wherein said CVD and back-sputtering step uses constituent gasses silane, O₂, and argon.

18. The method of claim 7, wherein at least one of said conducting regions is a non-reticulated conductor.

11. A method of constructing a planarized dielectric over a patterned conductor and adjacent regions on a semiconductor device, said method comprising:

(a) depositing a first layer of conducting material on a substrate;

(b) removing said first layer of conducting material in a circumscribing region upon said substrate, thereby defining a location for and peripheral walls for said conductor;

(c) removing said first layer of conducting material from at least one region within said circumscribing region to form internal and/or notch walls for said conductor, thereby dividing current-carrying capability for said conductor amongst at least two integrally-formed conducting segments of smaller minimum horizontal dimension than said conductor;

(d) forming an insulating layer over said conductor and said substrate by a deposition method which selectively planarizes features in order of smallest to largest based on minimum horizontal dimension; and

(e) depositing and patterning a second layer of conducting material overlying said insulating layer.

12. The method of claim 11, wherein said forming an insulating layer step comprises depositing silicon dioxide by a method of simultaneous CVD and back-sputtering.

13. The method of claim 12, further comprising depositing an insulating seed layer over said conductor and said substrate, prior to said depositing silicon dioxide by a method of simultaneous CVD and back-sputtering step.

14. The method of claim 11, further comprising depositing a CVD insulating layer over said conductor and said substrate, subsequent to forming step (d).

15. The method of claim 11, further comprising chemical-mechanical polishing said insulating layer.

16. The method of claim 11, wherein said conducting segments are formed to minimum design rule specifications for said semiconductor device.

17. The method of claim 11, wherein steps (b) and (c) are performed simultaneously.