Power semiconductor device having improved reverse recovery voltage

• US 5,686,750 A
• Filed: 04/29/1996
• Issued: 11/11/1997
• Est. Priority Date: 09/27/1991
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Koshiba & Partners
• Inventors: Takahashi, Mitsuasa
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/639,433
• Time in Patent Office: 561 Days
• Field of Search: 257/328, 257/334, 257/337, 257/339, 257/409, 257/329
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A vertical field effect transistor comprises a MOSFET cell zone which is formed in a principal surface of an N-type semiconductor substrate and in which a plurality of MOSFET cells are formed and connected in parallel with one another. A gate electrode pad and a source electrode pad are formed in the principal surface of the semiconductor substrate, separately from the MOSFET cell zone. A drain electrode pad is formed on a rear surface of the semiconductor substrate. A plurality of diodes are formed in the principal surface of the semiconductor substrate and arranged to form at least one array of diodes along an outer periphery of the MOSFET cell zone. An N-type region of each of the diodes is formed of the N-type semiconductor substrate itself and a P-type region of each of the diodes is connected to an electrode which is connected to a source electrode of the MOSFET cells.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a source electrode pad and a gate electrode pad for making external connections, said pads being located on a principal surface of said semiconductor substrate, said source electrode pad and gate electrode pad being separate from each other;

a drain electrode formed to cover a rear surface of said semiconductor substrate;

a cell zone formed in said principal surface at a location which is separate from said source electrode pad and said gate electrode pad;

an insulating film on said principal surface of said semiconductor substrate;

contact holes formed through said insulating film;

a plurality of vertical MOSFET cells formed in said cell zone and connected in parallel with one another;

each of said vertical MOSFET cells including a drain region which is formed of said semiconductor substrate, in common with all of said vertical MOSFET cells;

each of said cells further including a base region which is of a second conductivity type opposite to said first conductivity type and which is formed in said semiconductor substrate, each of said base regions being separate from the base regions of the other vertical MOSFET cells;

a source region of said first conductivity type formed in each of said base regions; and

a gate electrode formed adjacent to an individually associated one of said contact holes in said insulating film at least above each of said base regions and between the corresponding source region and said drain region;

a channel created in a surface area of each of said base regions and between said corresponding source region and said drain region;

each of said channels being controlled by an associated one of said gate electrodes;

said source region of each of said vertical MOSFET cells being connected to a source electrode via an individually associated contact hole formed in said insulating film, said source electrode being connected to said source electrode pad;

said gate electrode of each of said vertical MOSFET cells being connected to said gate electrode pad; and

a plurality of diode cells formed in said semiconductor substrate and arranged to form only one array of diode cells along at least one portion of an outer periphery of said cell zone;

each of said diode cells having a first region of said first conductivity type formed of said semiconductor substrate and a second region of said second conductivity type formed in said semiconductor substrate;

each of said second regions being separate from said second regions of the other diode cells and said base regions of said vertical MOSFET cells, and which is connected with said regions of the other diode cells and said base regions of said vertical MOSFET cells only with said source electrode via an individually associated contact hole formed in said insulating film;

said second region of each of said diode cells and said base regions of said vertical MOSFET cells having the same impurity concentration and depth so that said diode cells and said vertical MOSFET cells have the same breakdown voltage, said second regions of said diode cells and said base regions of said vertical MOSFET cells being located at the same constant intervals so that said diode cells and said vertical MOSFET cells are located equal intervals; and

said diode cells preventing a breakdown caused by a turn-on of a parasitic bipolar transistor of said MOSFET cells.

2. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a source electrode pad and a gate electrode pad for making external connections, said pads being located on a principal surface of said semiconductor substrate, said source electrode pad and gate electrode pad being separate from each other;

a drain electrode formed to cover a rear surface of said semiconductor substrate;

a cell zone formed in said principal surface at a location which is separate from said source electrode pad and said gate electrode pad;

an insulating film on said principal surface of said semiconductor substrate;

contact holes formed through said insulating film;

a plurality of vertical MOSFET cells formed in said cell zone and connected in parallel with one another;

each of said vertical MOSFET cells including a drain region which is formed of said semiconductor substrate, in common with all of said vertical MOSFET cells;

each of said cells further including a base region which is of a second conductivity type opposite to said first conductivity type and which is formed in said semiconductor substrate, each of said base regions being separate from the base regions of the other vertical MOSFET cells;

a source region of said first conductivity type formed in each of said base region; and

a gate electrode formed adjacent to an individually associated one of said contact holes in said insulating film at least above each of said base regions and between the corresponding source region and said drain region;

a channel created in a surface area of each of said base regions and between said corresponding source region and said drain region;

each of said channels being controlled by an associated one of said gate electrodes;

said source region of each of said vertical MOSFET cells being connected to a source electrode via an individually associated contact hole formed in said insulating film, said source electrode being connected to said source electrode pad;

said gate electrode of each of said vertical MOSFET cells being connected to said gate electrode pad; and

a plurality of diode cells formed in said semiconductor substrate and arranged to form only one array of diode cells along at least one portion of an outer periphery of said cell zone;

each of said diode cells having a first region of said first conductivity type formed of said semiconductor substrate and a second region of said second conductivity type formed in said semiconductor substrate;

each of said second regions being separate from said second regions of the other diode cells and said base regions of said vertical MOSFET cells, and which is connected with said second regions of the other diode cells and said base regions of said vertical MOSFET cells only with said source electrode via an individually associated contact hole formed in said insulating film;

said second region of each of said diode cells and said base regions of said vertical MOSFET cells having the same impurity concentration and depth so that said diode cells and said vertical MOSFET cells have the same breakdown voltage, said second regions of said diode cells and said base regions of said vertical MOSFET cells being located at the same constant intervals so that said diode cells and said vertical MOSFET cells are located equal intervals; and

said diode cells preventing a breakdown caused by a turn-on of a parasitic bipolar transistor of said MOSFET cells;

the semiconductor device further including a peripheral zone formed to extend along a periphery of said semiconductor substrate so as to surround said cell zone, said source electrode pad and said gate electrode pad;

said peripheral zone including a region formed in said principal surface of said semiconductor substrate so as to extend along the periphery of said semiconductor substrate, said peripheral zone region being of a conductivity type opposite to that of said semiconductor substrate;

a field plate formed on said principal surface of said semiconductor substrate so as to extend along the periphery of said semiconductor substrate, said field plate being connected to said peripheral zone region; and

a gate finger formed so that it is surrounded by said field plate and on said principal surface of said semiconductor substrate so as to extend along the periphery of said semiconductor substrate, said gate finger being connected to said gate electrode pad; and

wherein all of said plurality of diodes are arranged to form said only one array of diodes which extends along said outer periphery of said cell zone so as to extend along an outer periphery of said gate electrode pad and along an inner periphery of said peripheral zone.