Method and apparatus for controlling a voltage controlled oscillator tuning range in a frequency synthesizer

• US 5,686,864 A
• Filed: 09/05/1995
• Issued: 11/11/1997
• Est. Priority Date: 09/05/1995
• Status: Expired due to Term

• Current Assignee: Quarterhill Inc. (f/k/a Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Martin, Frederick L., Carralero, Cesar W.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US08/523,452
• Time in Patent Office: 798 Days
• Field of Search: 331/2, 331/DIG. 2, 331/57, 331/14, 331/1 A, 331/17, 331/10, 331/179, 327/107, 327/159, 327/160, 327/108 C
• US Class Current: 331/1.00A
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/103 the additional signal being a digital signal
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

A frequency synthesizer (100, 500) provides multiple selectable voltage controlled oscillator (VCO) frequency ranges. A VCO control circuit (114) controls the selectable VCO frequency ranges based on lock conditions of selected VCOs within a VCO array (112) or a single variable VCO circuit (502), to provide an extended tuning range to the frequency synthesizer (100, 500).

Claims

1. A phase lock loop (PLL) for a frequency synthesizer, comprising:

a reference oscillator providing a first frequency input signal;

a phase detector for comparing the phase of the first frequency input signal to a second frequency input signal and generating an error signal;

a loop filter coupled to said phase detector, said loop filter providing a control voltage in response to the error signal;

a plurality of voltage controlled oscillator (VCO) circuits receiving the control voltage;

a VCO control circuit for individually enabling and disabling each of the plurality of VCO circuits, said plurality of VCO circuits each individually generating an output frequency in response to being-enabled, the VCO control circuit including a delay means for determining the settling time of each individually enabled VCO circuit;

a lock detect circuit for determining, based on the control voltage, if the frequency synthesizer has locked on frequency with one of the plurality of VCO circuits, said VCO control circuit ceasing to individually enable and disable each of the plurality of VCO circuits once the frequency synthesizer has locked on frequency; and

a loop divider for dividing each generated output frequency by a predetermined amount and feeding a divided frequency back to the phase detector as the second frequency input signal.

2. A phase lock loop (PLL) for a frequency synthesizer as described in claim 1, wherein the VCO control circuit includes a counter for tracking the number of each individually enabled VCO circuit, said VCO control circuit being disabled once the number reaches a predetermined overflow limit.

3. A phase lock loop (PLL) for a frequency synthesizer as described in claim 1, wherein the VCO control circuit individually enables and disables each of the plurality of VCO circuits in a non-sequential manner.

4. A phase lock loop (PLL) for a frequency synthesizer, comprising:

a reference oscillator providing a first frequency input signal;

a phase detector for comparing the phase of the first frequency input signal to a second frequency input signal and generating an error signal;

a loop filter coupled to said phase detector, said loop filter providing a control voltage in response to the error signal;

a plurality of voltage controlled oscillator (VCO) circuits receiving the control voltage;

a VCO control circuit for individually enabling and disabling each of the plurality of VCO circuits, said plurality of VCO circuits each individually generating an output frequency in response to being enabled;

a lock detect circuit for determining, based on the control voltage, if the frequency synthesizer has locked on frequency with one of the plurality of VCO circuits, said VCO control circuit ceasing to individually enable and disable each of the plurality of VCO circuits once the frequency synthesizer has locked on frequency;

a loop divider for dividing each generated output frequency by a predetermined amount and feeding a divided frequency back to the phase detector as the second frequency input signal; and

wherein the lock detect circuit compares the control voltage to predetermined threshold limits to generate a lock indicator signal, the lock indicator signal indicating either a locked or unlocked synthesizer condition, said VCO control circuit individually enabling and disabling each of the plurality of VCO circuits in response to the lock indicator signal indicating an unlocked condition.

5. A phase lock loop (PLL) for a frequency synthesizer, comprising:

a reference oscillator providing a first frequency input signal;

a phase detector for comparing the phase of the first frequency input signal to a second frequency input signal and generating an error signal;

a loop filter coupled to said phase detector, said loop filter providing a control voltage in response to the error signal;

a plurality of voltage controlled oscillator (VCO) circuits receiving the control voltage;

a lock detect circuit responsive to the control voltage for generating a lock detect signal indicating a locked condition or an unlocked condition of the PLL;

a VCO control circuit responsive to the lock detect signal for selectively enabling and disabling each of the plurality of VCO circuits, one at a time, until a locked condition is indicated by the lock detect signal, the VCO control circuit ceasing to selectively enable and disable each of the plurality of VCO circuits when each of the plurality of VCO circuits has been selectively enabled without a locked condition being indicated by the lock detect signal;

the plurality of VCO circuits each providing a selectively generated output frequency in response to being enabled; and

a loop divider for dividing each selectively generated output frequency by a predetermined amount anal feeding a divided output frequency back to the phase detector as the second frequency input signal.

6. A phase lock loop (PLL) for a frequency synthesizer as described in claim 5, wherein the plurality of VCO circuits provide partially overlapping frequency ranges.

7. A voltage controlled oscillator (VCO) tuning circuit for a frequency synthesizer, including:

a plurality of VCOs, each providing different and partially overlapping frequency ranges, said plurality of VCOs each generating an output frequency in response to being enabled;

a VCO control circuit alternately enabling and disabling each of said plurality of VCOs to provide a tuning range within which the frequency synthesizer can lock on frequency; and

wherein the VCO control circuit includes a means for tracking the number of each alternately enabled VCO, said VCO control circuit being disabled in response to the number reaching a predetermined overflow limit.

8. A VCO tuning circuit for a frequency synthesizer as described in claim 7, wherein the frequency synthesizer locks on frequency with one of the alternately enabled VCOs, and the VCO control circuit ceases alternately enabling and disabling the plurality of VCOs once the frequency synthesizer locks on frequency.

9. A VCO tuning circuit for a frequency synthesizer as described in claim 7, further including:

a lock detect circuit for determining whether the frequency synthesizer has locked on frequency with one of the plurality of VCOs, said lock detect circuit generating a lock indicator signal indicating either a locked or unlocked condition of the frequency synthesizer, said VCO control circuit alternately enabling and disabling each of the plurality of VCOs when an unlocked condition is indicated, and said VCO control circuit terminating the alternate enabling and disabling of the plurality of VCOs when a locked condition is indicated.

10. A VCO tuning circuit for a frequency synthesizer as described in claim 7, wherein the VCO control circuit includes a delay circuit for maintaining each alternately enabled VCO enabled for a predetermined time.

11. A method of tuning a frequency synthesizer to lock on to a frequency, comprising the steps of:

generating a control voltage;

providing the control voltage to a plurality of voltage controlled oscillator (VCO) circuits having different yet overlapping frequency ranges;

alternately enabling and disabling each of the plurality VCO circuits;

alternately generating an output frequency from each of the alternately enabled VCO circuits in response to the control voltage;

determining if the frequency synthesizer has locked on frequency with each alternately generated output frequency; and

ceasing the alternate enabling and disabling of the plurality of VCO circuits once the frequency synthesizer has locked on frequency; and

wherein the step of determining further includes the steps of;

incrementing a counter when the frequency synthesizer fails to lock on frequency with the alternately generated output frequency; and

terminating the alternate enabling and disabling of the plurality of VCO circuits once the counter reaches a predetermined overflow limit.

12. A method of tuning a phase lock loop (PLL) in a frequency synthesizer, comprising the steps of:

providing a plurality of selectable voltage controlled oscillator (VCO) frequency ranges;

automatically selecting a VCO frequency from the plurality of selectable VCO frequency ranges;

attempting to lock the PLL on frequency with the selected VCO frequency;

checking whether the PLL has locked on frequency with the selected VCO frequency;

automatically de-selecting the selected VCO frequency after a predetermined time within which the PLL fails to lock on frequency;

repeating in a non-sequential manner the step of automatically selecting through the step of de-selecting until one of the plurality of selectable VCO frequency ranges locks the PLL on the selected VCO frequency; and

ceasing the step of repeating when a predetermined number of attempts to lock the PLL on frequency have been made.

13. A method of tuning a PLL in a frequency synthesizer as described in claim 12, wherein the plurality of selectable VCO frequency ranges are partially overlapping.

14. A phase lock loop (PLL) for a frequency synthesizer, comprising:

a reference oscillator providing a first frequency input signal;

a phase detector for comparing the phase of the first frequency input signal to a second frequency input signal and generating an error signal;

a loop filter coupled to said phase detector, said loop filter providing a control voltage in response to the error signal;

a plurality of voltage controlled oscillator (VCO) circuits receiving the control voltage;

a VCO control circuit for individually enabling and disabling each of the plurality of VCO circuits, said plurality of VCO circuits each individually generating an output frequency in response to being enabled, the VCO control circuit including a counter for tracking the number of each individually enabled VCO circuit, said VCO control circuit being disabled once the number reaches a predetermined overflow limit;

a lock detect circuit for determining, based on the control voltage, if the frequency synthesizer has locked on frequency with one of the plurality of VCO circuits, said VCO control circuit ceasing to individually enable and disable each of the plurality of VCO circuits once the frequency synthesizer has locked on frequency; and

a loop divider for dividing each generated output frequency by a predetermined amount and feeding a divided frequency back to the phase detector as the second frequency input signal.