Method for performing rate control in a video encoder which provides a bit budget for each frame while employing virtual buffers and virtual buffer verifiers

• US 5,686,963 A
• Filed: 12/26/1995
• Issued: 11/11/1997
• Est. Priority Date: 12/26/1995
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: C-Cube Corporation (Broadcom, Inc.)
• Inventors: Wells, Aaron, Uz, K. Metin
• Primary Examiner(s): Chin, Tommy P.
• Assistant Examiner(s): VINCENT, DAVID ROBERT
• Application Number:
  US08/578,811
• Time in Patent Office: 686 Days
• Field of Search: 348/423, 348/419, 348/405, 348/717, 348/718, 348/404, 348/410-411, 348/384, 348/390, 348/409
• US Class Current: 375/240.06
• CPC Class Codes: H04N 19/105 Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
• CPC Class Codes: H04N 19/107 between spatial and temporal predictive coding, e.g. picture refresh
• CPC Class Codes: H04N 19/112 according to a given display mode, e.g. for interlaced or progressive display mode
• CPC Class Codes: H04N 19/137 Motion inside a coding unit, e.g. average field, frame or block difference
• CPC Class Codes: H04N 19/14 Coding unit complexity, e.g. amount of activity or edge presence estimation H04N19/146 takes precedence
• CPC Class Codes: H04N 19/142 Detection of scene cut or scene change
• CPC Class Codes: H04N 19/146 Data rate or code amount at the encoder output
• CPC Class Codes: H04N 19/147 according to rate distortion criteria rate-distortion as a criterion for motion estimation H04N19/567
• CPC Class Codes: H04N 19/149 by estimating the code amount by means of a model, e.g. mathematical model or statistical model
• CPC Class Codes: H04N 19/15 by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
• CPC Class Codes: H04N 19/152 by measuring the fullness of the transmission buffer
• CPC Class Codes: H04N 19/17 the unit being an image region, e.g. an object
• CPC Class Codes: H04N 19/194 involving only two passes
• CPC Class Codes: H04N 19/30 using hierarchical techniques, e.g. scalability H04N19/63 takes precedence
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/53 Multi-resolution motion estimation; Hierarchical motion estimation
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/23406 involving management of server-side video buffer
• CPC Class Codes: H04N 21/2365 Multiplexing of several video streams
• CPC Class Codes: H04N 21/23655 Statistical multiplexing, e.g. by controlling the encoder to alter its bitrate to optimize the bandwidth utilization
• CPC Class Codes: H04N 21/2401 : Monitoring of the client buffer
• CPC Class Codes: H04N 21/4347 : Demultiplexing of several video streams
• CPC Class Codes: H04N 21/44004 : involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 21/6377 : directed to server one-way streaming services wherein the source is controlled by the destination H04L65/613
• CPC Class Codes: H04N 21/658 : Transmission by the client directed to the server

Abstract

A rate control algorithm for an MPEG-2 compliant encoder. The rate control has embodiments useful for constant bit rate and variable bit rate encoding of video frames. The present invention relates to statistical multiplexing, virtual buffers and virtual buffer verifiers.

Claims

1. In an encoder for encoding an input sequence of video frames to generate a compressed bitstream, said encoder comprising an encoding circuit and an output buffer connected to the encoding circuit for receiving the compressed bitstream, a method for performing rate control comprising the steps of:

(1) maintaining a model of a decoder input buffer by a controller of said encoder, a fullness of said model decoder input buffer changing in a way which mirrors changes in a fullness of said encoder output buffer,

(2) providing a bit budget for each of said frames by said controller depending on whether said frame is an I, P, or B frame and depending on a rate R_eff at which bits are removed from said encoder output buffer, said rate R_eff being variable,

(3) said bit budget being determined for each frame such that a system delay given by Δ

=encoder output buffer fullness/R_eff +model decoder input buffer size/R_eff remains constant, whereby a change in R_eff is responded to by said encoder by changing the bit budget for one or more of said frames to cause a change in said encoder output buffer fullness to maintain said system delay as constant,

(4) said bit budget being determined for each frame such that the number of bits budgeted to each frame will not cause said model decoder input buffer to overflow or underflow,

wherein the bit budget allocated to each frame depends on an effective frame rate, said effective frame rate being an average over a time window of the number of frames per second, wherein some of said frames have a duration of two field periods and some of said frames have a duration of three field periods.