Integrated circuit module having on-chip surge capacitors

• US 5,687,109 A
• Filed: 06/27/1996
• Issued: 11/11/1997
• Est. Priority Date: 05/31/1988
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Johnson, Gary M., Parkinson, Ward D., Duesman, Kevin G., Nevill, Leland R., Chern, Wen-Foo, Protigal, Stanley N., Trent, Thomas M.
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US08/671,248
• Time in Patent Office: 502 Days
• Field of Search: 365/63, 365/51, 365/52, 365/149, 257/312, 257/532
• US Class Current: 365/63
• CPC Class Codes: G06F 11/1451 by selection of backup contents
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances

Abstract

A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on-chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the integrated circuit devices.

Claims

1. A semiconductor device system to be electrically connected to external circuitry, the system comprising:

a support surface having a first set of conductors electrically connected to each other, and a second set of conductors electrically connected to each other; and

a plurality of semiconductor devices supported by the support surface and each including;

a first contact electrically connected to one of the first set of conductors;

a second contact electrically connected to one of the second set of conductors;

a substrate of a first conductivity type;

active circuit devices on the substrate; and

a depletion mode on-chip capacitor including a conductive layer separated from the substrate by a dielectric, the capacitor including spaced apart first and second doped regions that are of a second conductivity type, and wherein the conductive layer is electrically connected to the first contact, and the first and second doped regions are electrically connected to the second contact such that the on-chip capacitor may provide filtering capacitance to the semiconductor device.

2. The system of claim 1, wherein the semiconductor devices are packaged semiconductor devices that include leads extending out of the packaging, and wherein the first and second contacts for each semiconductor device are internal to the packaging, and the first and second contacts are electrically connected to the first and second set of conductors through ones of the leads.

3. The system of claim 1, wherein the on-chip capacitors provide capacitive decoupling of the semiconductor device system with respect to the external circuitry.

4. The system of claim 1, wherein the semiconductor devices further include conductive data lines positioned over the on-chip capacitors.

5. The system of claim 1, wherein the conductive layers are polysilicon layers.

6. The system of claim 1, wherein the semiconductor devices are a first set of semiconductor devices and the system further comprises additional semiconductor devices not connected in parallel with the first set of semiconductor devices.

7. The system of claim 1, wherein the first set of conductors are electrically connected through a bus on which a VCC signal may be provided.

8. The system of claim 1, wherein the second set of conductors are electrically connected through a bus on which a VSS signal may be provided.

9. The system of claim 1, wherein the first contacts conduct a VCC signal.

10. The system of claim 1, wherein the second contacts conduct a VSS signal.

11. The system of claim 1, wherein the first contacts include bonding pads.

12. The system of claim 1, wherein the first contacts include lead fingers.

13. The system of claim 1, wherein the first contacts are electrically connected to one of the first set of conductors through lead fingers.

14. The system of claim 1, wherein the plurality is two semiconductor devices.

15. The system of claim 1, wherein there are more than two semiconductor devices.

16. The system of claim 1, wherein the semiconductor devices are memory devices.

17. The system of claim 1, wherein the semiconductor devices are DRAM memory devices.

18. The system of claim 1, wherein the semiconductor devices are SIMM memory devices.

19. The system of claim 1, wherein the semiconductor devices are SIP memory devices.

20. A semiconductor device system to be electrically connected to external circuitry, the system comprising:

a support surface having a first set of conductors electrically connected to each other, and a second set of conductors electrically connected to each other; and

a plurality of semiconductor devices supported by the support surface and each including;

a first contact electrically connected to one of the first set of conductors;

a second contact electrically connected to one of the second set of conductors;

a substrate;

active circuit devices on the substrate; and

a depletion mode on-chip capacitor including a conductive layer separated from the substrate by a dielectric, the capacitor including a doped region and a more heavily doped region, and wherein the conductive layer is electrically connected to the first contact and wherein the more heavily doped region is connected to the second contact such that the on-chip capacitor may provide filtering capacitance to the semiconductor device.

21. The system of claim 20, wherein the on-chip capacitors provide capacitive decoupling of the semiconductor device system with respect to the external circuitry.

22. The system of claim 20, wherein the semiconductor devices further include conductive data lines positioned over the on-chip capacitors.

23. The system of claim 20, wherein the first contacts conduct a VCC signal.

24. The system of claim 20, wherein the second contacts conduct a VSS signal.

25. A semiconductor device system to be electrically connected to external circuitry, the system comprising:

a support surface having a first set of conductors electrically connected to each other, and a second set of conductors electrically connected to each other; and

a plurality of semiconductor devices supported by the support surface and each including;

a first contact electrically connected to one of the first set of conductors;

a second contact electrically connected to one of the second set of conductors;

a substrate;

active circuit devices on the substrate; and

an on-chip capacitor, a portion of which is formed in an active area of the substrate, the on-chip capacitor including a first node electrically connected to the first contact, and a second node electrically connected to the second contact such that the on-chip capacitor may provide filtering capacitance to the semiconductor device, and wherein the on-chip capacitors for the semiconductor devices are in parallel between the first and second sets of conductors.

26. The system of claim 25, wherein the semiconductor devices are packaged semiconductor devices that include leads extending out of the packaging, and wherein the first and second contacts for each semiconductor device are inside the packaging, and the first and second contacts are electrically connected to the first and second set of conductors through some of the leads.

27. The system of claim 25, wherein the on-chip capacitors provide capacitive decoupling of the semiconductor device system with respect to the external circuitry.

28. The system of claim 25, wherein the semiconductor devices further include conductive data lines positioned over the on-chip capacitors.

29. The system of claim 25, wherein each of the on-chip capacitors includes a conductive layer connected to the first node.

30. The system of claim 25, wherein each of the on-chip capacitors are depletion mode capacitors.

31. The system of claim 25, wherein each of the on-chip capacitors are enhancement mode capacitors.

32. The system of claim 25, wherein the first contacts conduct a power signal.

33. The system of claim 25, wherein at least some of the active circuit devices are electrically connected to the first node.

34. A semiconductor device system to be electrically connected to external circuitry, the system comprising:

a support surface having a first set of conductors electrically connected to each other, and a second set of conductors electrically connected to each other; and

semiconductor devices supported by the support surface and each including;

a first contact electrically connected to one of the first set of conductors to receive an electrical power signal therefrom;

a second contact electrically connected to one of the second set of conductors;

a regulator circuit electrically connected to the first contact;

a substrate;

active circuit devices on the substrate; and

an on-chip capacitor, a portion of which is formed in an active area of the substrate, the on-chip capacitor including a first node electrically connected to the regulator circuit, and a second node electrically connected to the second contact such that the on-chip capacitor may provide filtering capacitance to the semiconductor device.

35. The system of claim 34, wherein the semiconductor devices provide capacitive decoupling of the semiconductor device with respect to the external circuitry.

36. The system of claim 34, wherein each of the on-chip capacitors includes a conductive layer connected to the first node.

37. The system of claim 34, wherein the semiconductor devices further include conductive data lines positioned over the on-chip capacitors.

38. The system of claim 34, wherein each of the on-chip capacitors are depletion mode capacitors.

39. The system of claim 34, wherein each of the on-chip capacitors are enhancement mode capacitors.