Electrically programmable memory cell

• US 5,687,113 A
• Filed: 03/28/1995
• Issued: 11/11/1997
• Est. Priority Date: 03/30/1994
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics SA (STMicroelectronics NV)
• Original Assignee: SGS Thomson Microelectronics SA (STMicroelectronics NV)
• Inventors: Guillaumot, Bernard, Papadas, Constantin
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/413,206
• Time in Patent Office: 959 Days
• Field of Search: 365/185, 365/189.01, 365/230.01, 365/189.02, 365/189.03, 365/189.04, 365/185.01, 365/185.05, 365/185.18
• US Class Current: 365/185.01
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 2211/5612 Multilevel memory cell with more than one floating gate
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Abstract

An electrically programmable cell comprises a substrate of the first conductivity type having a channel region, a control gate on a first insulating layer above the channel region, a source region and a drain region of a second conductivity type, on both sides of the channel region, at least the drain region including a low-doped region adjacent to the channel, a floating gate on a second insulating layer above at least a portion of said low-doped region. The thickness of the second insulating layer is lower than the thickness of the first insulating layer and is low enough for having charge transfers through tunnel effect.

Claims

1. Electrically programmable cell comprising:

a substrate of a first conductivity type, having a channel region having a first side and a second side;

a control gate located on a first insulating layer above the channel region;

a drain region of a second conductivity type located on the substrate adjacent to the first side of the channel region, the drain region having a low-doped region adjacent to the channel region;

a source region of the second conductivity type located on the substrate adjacent to the second side of the channel region;

an insulated floating gate located on a second insulating layer above a portion of the drain region, the insulated floating gate being disposed such that it does not extend over the channel region.

2. The memory cell of claim 1, wherein the source region includes a low-doped region adjacent to the channel region, and wherein the insulated floating gate is located on the low-doped area of the drain region and the low-doped area of the source region.

3. The memory cell of claim 2, wherein the insulated floating gate encircles the control gate.

4. The memory cell of claim 3, wherein the second insulating layer has a thickness ranging from 8 nm to 12 nm.

5. The memory cell of claim 4, further comprising a second insulating layer disposed beneath the control gate, said second insulating layer made of silicon oxide having a thickness of approximately 20 nm.

6. The memory cell of claim 2, wherein the second insulating layer has a thickness ranging from 8 nm to 12 nm.

7. The memory cell of claim 6, further comprising a second insulating layer disposed beneath the control gate, said second insulating layer made of silicone oxide having a thickness of approximately 20 nm.

8. The memory cell of claim 2, further comprising a second insulating layer disposed beneath the control gate, said second insulating layer made of silicone oxide having a thickness of approximately 20 nm.

9. The memory cell of claim 1, wherein the second insulating layer has a thickness ranging from 8 nm to 12 nm.

10. The memory cell of claim 9, further comprising a second insulating layer disposed beneath the control gate, said second insulating layer made of silicon oxide having a thickness of approximately 20 nm.

11. The memory cell of claim 1, further comprising a second insulating layer disposed beneath the control gate, said second insulating layer made of silicon oxide having a thickness of approximately 20 nm.

17. The electrically programmable cell of claim 1, wherein the insulated floating gate is disposed over only the low doped region of the drain region.

12. An electrically programmable cell comprising:

a substrate of a first conductivity type having a semiconductor face including a channel region, the channel region having first and second sides and an upper surface;

a first insulating layer disposed over the channel region;

a control gate disposed over the first insulating layer and disposed over the upper surface of the channel region of the semiconductor face;

a drain region of a second conductivity type disposed over the semiconductor face adjacent the first side of the channel region;

a source region of the second conductivity type disposed over the semiconductor face adjacent to the second side of the channel region;

an insulated floating gate disposed over the semiconductor face such that the insulated floating gate encircles the control gate; and

a second insulating layer disposed between the drain region and the insulated floating gate.

13. The electrically programmable cell of claim 12, wherein the drain region includes a low-doped region adjacent the first side of the channel region.

14. The electrically programmable cell of claim 13, wherein the source region includes a low-doped region adjacent to the second side of the channel region.

15. The electrically programmable cell of claim 14, wherein the insulated gate is disposed over only the low-doped region of the drain region and the low-doped region of the source region.

16. The electrically programmable cell of claim 12, a thickness of the first insulating layer is greater than a thickness of the second insulating layer.