Method and circuit for supplying memory IC power

• US 5,687,129 A
• Filed: 04/29/1996
• Issued: 11/11/1997
• Est. Priority Date: 04/27/1995
• Status: Expired due to Term

• Current Assignee: LG Semicon Co Ltd (SK Hynix Inc.)
• Original Assignee: LG Semicon Co Ltd (SK Hynix Inc.)
• Inventors: Kim, Myoung-Kee
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): LE, VU ANH
• Application Number:
  US08/639,465
• Time in Patent Office: 561 Days
• Field of Search: 365/229, 365/228, 365/227, 365/226
• US Class Current: 365/229
• CPC Class Codes: G11C 5/141 Battery and back-up supplies

Abstract

A circuit for supplying power to an IC memory card by using primary and secondary batteries as a data preserving power means for the memory IC according to the present invention, includes: primary and secondary batteries; a secondary battery charging circuit for charging the secondary battery; and a primary and secondary battery backup circuit for connecting the primary and secondary batteries to the memory IC when an external power source is disconnected; a serial-parallel switching means for connecting the primary and secondary batteries in series or in parallel; a voltage detecting means for comparing a power voltage of the memory IC with a reference voltage to generate a voltage detection signal upon finding the power voltage dropped to below the reference voltage; and a switching control means for receiving the voltage detection signal of the voltage detecting means to control the serial-parallel switching means so as to connect the primary and secondary batteries in series or in parallel.

Claims

1. A circuit for supplying power to an IC memory, said circuit including a reserve power supply having primary and secondary batteries;

a secondary battery charging circuit for charging said secondary battery; and

a primary and secondary battery backup circuit for providing power and voltage to the IC memory when an external power source providing external power and voltage is disconnected, the circuit further comprising;

switching means for connecting said primary and secondary batteries in series or in parallel;

voltage detecting means for comparing voltage provided to said IC memory with a reference voltage to generate a voltage detection signal when the provided voltage drops below a reference voltage; and

switching control means for receiving the voltage detection signal from said voltage detecting means to control said switching means;

wherein when said external power source is disconnected, the switching means connects said primary and secondary batteries in parallel if the voltage provided to the IC memory is not below the reference voltage level, and alternatively connects the primary and secondary batteries in series if the voltage provided to the IC memory drops below the reference voltage level.

2. The circuit of claim 1, wherein said voltage detecting means is a comparator.

3. The circuit of claim 1, wherein said switching means comprises:

a first switch connected between a negative terminal of said secondary battery and a ground line;

a second switch connected between a positive terminal of said primary battery and the negative terminal of said secondary battery; and

a third switch connected between a positive terminal of said secondary battery and a power terminal of said IC memory.

4. The circuit of claim 1, wherein said switching control means comprises:

a JK flip flop for receiving a voltage detection signal from said voltage detecting means through a clock input terminal, and for receiving an external power voltage through a reset terminal, so as output a high or low voltage level at an output terminal.

5. The circuit of claim 3, wherein said switching control means comprises:

a JK flip flop for receiving the voltage detection signal from said voltage detecting means through a clock input terminal, and for receiving an external power voltage through a reset terminal so as to output a high or low voltage level at an output terminal; and

wherein the output of the flip flop is connected to said second and third switches, and

the output of the flip flop is further connected through an invertor to said first switch.

6. The circuit of claim 3, wherein the first switch connects the secondary battery so that the primary and secondary batteries are in parallel first and second electrical paths, and the second and third switches connect the primary and secondary batteries in a serial third electrical path.

7. The circuit of claim 6, wherein:

the first electrical path includes a first ground voltage, the first switch, the secondary battery and a first diode connected to said IC memory;

the second electrical path includes a second ground voltage, the primary battery, a resistor and a second diode connected to said IC memory; and

the third electrical path includes the second ground voltage, the primary battery, the second switch, the secondary battery and the third switch connected to said IC memory.

8. A method for supplying power to an IC memory, said circuit including a reserve power supply including primary and secondary batteries, a secondary battery charging circuit for charging said secondary battery, and a primary and secondary battery backup circuit for connecting said primary and secondary batteries to the IC memory, said method comprising the steps of:

providing power and operating voltage from said secondary battery to said IC memory along a first electrical path when primary power to said IC memory is discontinued;

providing power and operating voltage from said primary battery to said IC memory along a second electrical path and in parallel providing power and operating voltage from said secondary battery to said IC memory along the first electrical path when primary power to said IC is discontinued, and voltage supplied by said secondary battery falls below a voltage level supplied by said primary battery;

providing power and operating voltage from said primary battery and said secondary battery along a third electrical path to said IC memory when primary power to said IC is discontinued and the voltage supplied by said primary and secondary batteries falls below a reference level, wherein the primary and second batteries are connected in series in the third electrical path.

9. The method of claim 8, wherein a first switch is used for electrically connecting only the first and second electrical paths to the IC memory to provide power and voltage when the voltage supplied by said primary and secondary batteries exceeds a reference level, and second and third switches are used for electrically connecting only the third electrical path to said IC memory to provide power and voltage when the voltage supplied by said primary and secondary batteries falls below a reference level.

10. The method of claim 9, further comprising the steps of:

comparing the voltage supplied to said IC memory by said primary and secondary batteries with a reference voltage, and generating a voltage detection signal when the IC memory voltage drops below the reference voltage.

11. The method of claim 10, wherein a switching control means receives the voltage detection signal and controls the first, second and third switches so as to connect the IC memory to the first and second electrical paths when the voltage detection signal is one logic level, and to connect the IC memory to the third electrical path when the voltage detection signal is a second logic level.

12. A circuit for supplying power to an IC memory, said circuit including a reserve power supply including primary and secondary batteries, a second battery charging circuit for charging said secondary battery, and a primary and secondary battery backup circuit for connecting said primary and secondary batteries to the IC memory, the circuit further comprising:

a first electrical path for providing power and operating voltage to said IC memory from said secondary battery when primary power to said IC memory is discontinued;

a second electrical path for providing power and operating voltage to said IC memory from said primary battery when primary power to said IC memory is discontinued, and voltage supplied by said secondary battery falls below a voltage level supplied by said primary battery;

a third electrical path for providing power and operating voltage to said IC memory from both of said primary and secondary batteries in series when primary power to said IC memory is discontinued and the voltage supplied by said primary and second batteries falls below a reference level.

13. The circuit of claim 12, further including a first switch for electrically connecting only the first and second electrical paths to the IC memory to provide power and voltage when the combined voltage supplied by said primary and secondary batteries exceeds a reference level, and second and third switches for electrically connecting only the third electrical path to said IC memory to provide power and voltage when the combined voltage supplied by said primary and secondary batteries falls below a reference level.

14. The circuit of claim 12, further comprising a voltage detecting means for comparing a voltage supplied to said IC memory by said primary and secondary batteries with a reference voltage, and for generating a voltage detection signal when the voltage supplied to the IC memory drops below the reference voltage.

15. The circuit of claim 14, further including a switching control means for receiving the voltage detection signal from said voltage detecting means, and for controlling the first, second and third switches so as to connect the IC memory to the first and second electrical paths when the voltage detection signal is one logic level, and to connect the IC memory to the third electrical path when the voltage detection signal is a second logic level.

16. The circuit of claim 13, wherein the first switch connects the primary and secondary batteries in parallel in the first and second electrical paths, and the second and third switches connect the primary and secondary batteries in series in the third electrical path.

17. The circuit of claim 14, wherein said voltage detecting means is a comparator.

18. The circuit of claim 15, wherein:

the first switch is connected between a negative terminal of said secondary battery

and a ground line;

the second switch is connected between a positive terminal of said primary battery and the negative terminal of said secondary battery; and

the third switch is connected between a positive terminal of said secondary battery and a power terminal of said memory IC.

19. The circuit of claim 15, wherein said switching control means comprises:

a JK flip flop having an input for receiving the voltage detection signal from the voltage detecting means through a clock input terminal, a reset input for receiving an external voltage from the primary power source, and an output for controlling the first, second and third switches; and

wherein when the voltage detection signal is one logical level, the JK output activates the first switch to connects the primary and secondary batteries in parallel through the first and second electrical paths, and when the voltage detection signal is a second logical level, the JK output activates the second and third switches to connects the primary and secondary batteries in serial through the third electrical path.

20. The circuit of claim 13, wherein:

the first electrical path includes a first ground voltage, the first switch, the secondary battery and a first diode connected to said IC memory;

the second electrical path includes a second ground voltage, the primary battery, a resistor and a second diode connected to said IC memory; and

the third electrical path includes the second ground voltage, the primary battery, the second switch, the secondary battery and the third switch connected to said IC memory.

21. A voltage circuit for a device including memory that receives a primary voltage from a primary power supply that may be connected and disconnected, comprising:

a first battery;

a second battery; and

a switch control circuit coupled to the first and second batteries and to the device, wherein the switch control circuit couples the first and second batteries in parallel to provide voltage to the device upon disconnection of the primary power supply, wherein the switch control circuit couples the first and second batteries in series to provide voltage to the device if the voltage provided to the device is below a reference voltage level.

22. The circuit of claim 21, further comprising a voltage detector circuit receiving the voltage provided to the device and the reference voltage, wherein the voltage detector circuit provides a voltage detection signal to the switch control circuit when the voltage provided to the device is below the reference voltage level.

23. The circuit of claim 21, further comprising a charging circuit coupled to the first battery, wherein the charging circuit provides a charging voltage to the first battery when the primary power supply is connected.

24. The circuit of claim 21, wherein the first and second batteries are each coupled to the device with diodes when coupled in parallel, and wherein the first and second batteries are coupled to the device without diodes when coupled in series.

25. The circuit of claim 21, wherein the switch control circuit comprises first, second and third switches, wherein the first switch is coupled to the first battery so that the first and second batteries are coupled to the device in parallel upon disconnection of the power supply, wherein the second and third switches couple the first and second batteries to the device in series if the voltage provided to the device is below a reference voltage level.

26. The circuit of claim 24, wherein the voltage supplied by the first battery is greater than the voltage supplied by the second battery.

27. A method for providing power to a device including memory that receives a primary voltage from a primary power supply that may be connected and disconnected, comprising the steps of:

coupling first and second batteries to the device if the primary power supply is disconnected, wherein the first and second batteries are coupled to the device in parallel if voltage provided to the device by the parallely coupled first and second batteries is not below a reference voltage level; and

coupling the first and second batteries to the device in series if the voltage provided to the device by the parallely coupled first and second batteries is below the reference voltage level.

28. The method of claim 27, further comprising the step of charging the first battery when the primary power supply is connected.

29. The method of claim 27, further comprising the step of comparing the voltage provided to the device by the parallely coupled first and second batteries to the reference voltage level, and generating a voltage detection signal if the voltage provided to the device is below the reference voltage level.

30. The method of claim 29, wherein the first and second batteries are coupled to the device in series in response to the voltage detection signal.