Non-coherent direct sequence spread spectrum receiver for detecting bit/symbol chip sequences using threshold comparisons of chip sequence correlations

• US 5,687,190 A
• Filed: 10/20/1995
• Issued: 11/11/1997
• Est. Priority Date: 10/20/1995
• Status: Expired due to Fees

• Current Assignee: OTC Telecom Corporation
• Original Assignee: OTC Telecom Corporation
• Inventors: Tsao, C. H. Alex
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Gluck, Jeffrey W.
• Application Number:
  US08/546,228
• Time in Patent Office: 753 Days
• Field of Search: 375/206, 375/207, 375/208, 375/209, 375/210, 375/343, 375/359
• US Class Current: 375/142
• CPC Class Codes: H04B 1/707 using direct sequence modulation

Abstract

A method and apparatus for transmitting and receiving a direct sequence spread spectrum signal encoded using two or more chip sequences to encode an information signal. The encoded information signal is received using a bank of matched filters (501a-501l), a bank of threshold comparators (505a-505l), a non-frequency locked bit clock circuit (509, 509'"'"') and a bit detector (510). Frequency locking is avoided by performing correlation on both the I- and Q- baseband signals and by logically combining the correlation results to recover the bit clock. In one embodiment, the method and apparatus uses binary phase shift keying to modulate the direct sequence spread spectrum signal with a carrier. In another embodiment, quadrature phase shift keying is used.

Claims

1. A method for recovering a digital signal comprising a sequence of bits having a first and second state from a direct sequence spread spectrum phase shift keyed signal wherein each bit in the first state is substituted by one of a first set of chip sequences and each bit in the second state substituted by a one of a second set of chip sequences, the method comprising the steps of:

demodulating the direct sequence spread spectrum signal to form an in-phase baseband signal and a quadrature-phase baseband signal;

correlating the in-phase baseband signal with each chip sequence of the first set of chip sequences to generate a first set of correlation values;

correlating the in-phase baseband signal with each chip sequence of the second set of chip sequences to generate a second set of correlation values;

correlating the quadrature-phase baseband signal with each chip sequence of the first set of chip sequences to generate a third set of correlation values;

correlating the quadrature-phase baseband signal with each chip sequence of the second set of chip sequences to generate a fourth set of correlation values;

comparing each correlation value to a corresponding threshold value;

responsive to any of the first and third correlation values being greater than the corresponding threshold values, indicating a first bit state detection; and

responsive to any of the second and fourth correlation values being greater than the corresponding threshold values, indicating a second bit state detection.

2. The method of claim 1 wherein the phase shift keyed signal is a binary phase shift keyed signal.

3. The method of claim 1 wherein the phase shift keyed signal is a quadrature phase shift keyed signal.

4. A method for recovering a digital signal comprising a sequence of bits having a first and second state from a direct sequence spread spectrum binary phase shift keyed (BPSK) signal wherein each bit in the first state is substituted by a first chip sequence and each bit in the second state is substituted by a second chip sequence, the method comprising the steps of:

demodulating the direct sequence spread spectrum BPSK signal to form an in-phase baseband signal and a quadrature-phase baseband signal;

correlating the in-phase baseband signal with the first and second chip sequences to generate a first and a second correlation value respectively;

correlating the quadrature-phase baseband signal with the first and second chip sequence to generate a third and a fourth correlation value respectively;

comparing each correlation value to a corresponding threshold value;

responsive to either of the first and third correlation values being greater than the corresponding threshold values, indicating a first bit state detection; and

responsive to either of the second and fourth correlation values being greater than the corresponding threshold values, indicating a second bit state detection.

5. The method of claim 4 wherein the steps of indicating a first bit state detection and indicating a second bit state detection comprise the steps of:

responsive to any of the correlation values being greater than the corresponding threshold values, generating a symbol clock pulse;

responsive to either of the first and third correlation values being greater than the corresponding threshold value, generating a first bit state detect pulse;

responsive to any of the second and fourth correlation values being greater than the corresponding threshold value, generating a second bit state detect pulse;

for each symbol clock pulse, detecting one of the first and second bit state detect pulses;

setting an output signal to the first bit state responsive to detection of the first bit state detect pulse; and

setting an output signal to the second bit state responsive to detection of the second bit state detect pulse.

6. A method for recovering a digital signal comprising a sequence of interleaved I-Channel and Q-Channel bits, each having a first and second state, from a direct sequence spread spectrum quadrature phase shift keyed (QPSK) signal wherein each I-Channel bit in the first state is substituted by a first chip sequence, each I-Channel bit in the second state is substituted by a second chip sequence, each Q-Channel bit in the first state is substituted by a third chip sequence and each Q-Channel bit in the second state is substituted by a fourth chip sequence, the method comprising the steps of:

demodulating the direct sequence spread spectrum QPSK signal to form an in-phase baseband signal and a quadrature-phase baseband signal;

correlating the in-phase baseband signal with the first, second, third and fourth chip sequences to generate a first, a second, a third and a fourth correlation value respectively;

correlating the quadrature-phase baseband signal with the first, second, third and fourth chip sequences to generate a fifth, a sixth, a seventh and an eighth correlation value respectively;

comparing each correlation value to a corresponding threshold value;

responsive to any of the first, third, fifth, or seventh correlation values being greater than the corresponding threshold values, indicating a first bit state detection; and

responsive to any of the second, fourth, sixth, or eighth correlation values being greater than the corresponding threshold values, indicating a second bit state detection.

7. The method of claim 6 wherein the steps of indicating a first bit state detection and indicating a second bit state detection comprise the steps of:

responsive to any of the correlation values being greater than the corresponding threshold values, generating a symbol clock pulse;

responsive to either of the first and third correlation values being greater than the corresponding threshold value, generating a first bit state detect pulse;

responsive to any of the second and fourth correlation values being greater than the corresponding threshold value, generating a second bit state detect pulse;

for each symbol clock pulse, detecting one of the first and second bit state detect pulses;

setting an output signal to the first bit state responsive to detection of the first bit state detect pulse; and

setting an output signal to the second bit state responsive to detection of the second bit state detect pulse.

8. A method for transmitting and receiving a digital signal comprised of bits having first and second states, the method comprising the steps of:

substituting each bit having the first state with a first chip sequence and substituting each bit having a second state with a second chip sequence, to form a spread spectrum signal;

phase modulating a carrier wave with the spread spectrum signal to form a BPSK signal;

transmitting the BPSK signal;

receiving the transmitted BPSK signal;

mixing the received BPSK signal with a first sinusoid having substantially the same frequency as the carrier wave to form an in-phase baseband signal;

mixing the received BPSK signal with a second sinusoid having substantially the same frequency as the carrier wave and having a 90 degree phase shift relative to the first sinusoid to form a quadrature-phase baseband signal;

correlating the in-phase baseband signal with the first and second chip sequences to generate a first and a second correlation value respectively;

correlating the quadrature-phase baseband signal with the first and second chip sequence to generate a third and a fourth correlation value respectively;

comparing each correlation value to a corresponding threshold value;

responsive to either of the first and third correlation values being greater than the corresponding threshold values, indicating a first bit state detection; and

responsive to either of the second and fourth correlation values being greater than the corresponding threshold values, indicating a second bit state detection.

9. An apparatus for recovering an information signal from a digitized BPSK direct sequence spread spectrum signal having been downconverted by a non-coherent demodulator to form an in-phase signal on an in-phase channel and a quadrature-phase signal on a quadrature channel, the direct sequence spread spectrum signal being spread using a plurality of chip sequences, the apparatus comprising:

a bank of matched filters having a first plurality of inputs coupled to the in-phase channel and a second plurality of inputs coupled to the quadrature-phase channel, and having a plurality of outputs each having one of a plurality of states responsive to the degree of correlation between an associated input and an associated chip sequence;

a bank of threshold comparators each associated with a chip sequence, the bank having a plurality of inputs coupled to the plurality of matched filter outputs and a plurality of corresponding outputs each having a first state responsive to the corresponding input being greater than a predetermined value and a second state responsive to the corresponding input being less than a predetermined value;

a recovery circuit having a plurality of inputs coupled to the comparator outputs, the recovery circuit having a clock output being in a first state responsive to any one of the inputs being in the first state and being in a second state responsive to all of the inputs being in the second state, the recovery circuit further having a first symbol output being in a first state responsive to any one of the comparator outputs associated with the first chip sequence being in the first state and being in a second state responsive to each of the comparator outputs associated with the first chip sequence being in second state; and

a bit detection circuit having a plurality of inputs coupled to the recovery circuit outputs and having an output having a first state responsive to the first symbol being in the first state on a clock state transition and having a second state responsive to all of the inputs being in the second state on a clock state transition.

10. A non-coherent spread spectrum demodulator for coupling to a receiving path and for demodulating a direct sequence spread spectrum signal having a plurality of chip sequences, the demodulator comprising:

an in-phase mixer having an input and an output, the input coupled to the receiving path for converting the direct sequence spread spectrum signal to an in-phase baseband signal;

a quadrature-phase mixer having an input and an output, the input coupled to the receiving path for converting the direct sequence spread spectrum signal to a quadrature-phase baseband signal;

first and second analog-to-digital converters having inputs and outputs, the inputs coupled to the in-phase and quadrature-phase baseband mixer outputs respectively;

for each chip sequence, a matched filter having the associated chip sequence as a first input, having a second input coupled to the output of the first analog-to-digital converter and having a correlation output;

for each chip sequence, a matched filter having the associated chip sequence as a first input, having a second input coupled to the output of the second analog-to-digital converter and having a correlation output;

a plurality of threshold comparators each coupled to a correlation output and each associated with a chip sequence, each threshold comparator having a detect output having a first state responsive to the correlation output being greater than a predetermined value and having a second state responsive to the correlation output being less than the predetermined value;

for each chip sequence, a symbol detect circuit having a plurality of inputs coupled to the detect outputs of the comparators associated with the chip sequence, symbol detect circuit having an output being in a first state responsive to any one of the inputs being in the first state and being in a second state responsive to all of the inputs being in the second state;

a bit clock generator having inputs coupled to the symbol detect circuit outputs and having an output in a first state responsive to any of the inputs being in the first state and having a second state responsive to all of the inputs being in the second state; and

a bit generation circuit having an input coupled to the bit clock generator output and a plurality of inputs coupled to the symbol detect circuit outputs for multiplexing the symbol detect circuit outputs.