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Steganographic method and device

  • US 5,687,236 A
  • Filed: 12/31/1996
  • Issued: 11/11/1997
  • Est. Priority Date: 06/07/1995
  • Status: Expired due to Term
First Claim
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1. An apparatus for encoding or decoding independent information, including a digital watermark, represented as a series of data bits into or out of a series of digitized samples, comprising:

  • a) a sample buffer for holding, accessing and transforming digitized samples;

    b) a digital signal processor for performing sample modifications and spectral transformations;

    c) a memory for storing information representing;

    1) a mask set, including one or more masks,2) a start of message delimiter,3) a mask calculation buffer,4) a first buffer holding the independent information,5) an information bit index,6) a message size, representing an amount of information,7) one index into each of said one or more masks,8) a state of a decoding process,9) a table representing a map function,10) a flag indicating whether a complete message has been decoded or encoded,11) a number of samples for reading into said sample buffer, and12) a flag indicating a size of a message that has been decoded, wherein at least one of said one or more masks, or the start of message delimiter are random or pseudo-random;

    d) a first input for acquiring a plurality of digital samples;

    e) a first output for outputting a plurality of modified digital samples;

    f) a second input for inputting a plurality of values to the one or more masks, the start of message delimiter, the mask calculation buffer, the first buffer, the table and the number of samples;

    g) a third output for outputting the independent information stored in the first buffer as a result of the decoding process and a value of the state of the decoding process to an attached digital circuit;

    h) at least one data bus for transferring information from;

    1) the first input to the sample buffer,2) the sample buffer to the digital signal processor,3) the digital signal processor to the sample buffer,4) the sample buffer to the first output,5) the second input to the memory, and6) the memory to the third output; and

    l) a clock for generating a clock signal for driving the digital signal processor and the at least one data bus, and for controlling the operation of the apparatus.

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