Application specific field programmable gate array

• US 5,687,325 A
• Filed: 04/19/1996
• Issued: 11/11/1997
• Est. Priority Date: 04/19/1996
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Web Chang
• Inventors: Chang, Web
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Dharia, Rupal D.
• Application Number:
  US08/634,728
• Time in Patent Office: 571 Days
• Field of Search: 326/39, 326/40, 326/41, 364/488, 364/489, 364/490, 364/716, 340/825.83, 340/825.87, 395/800, 395/284
• US Class Current: 710/104
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns

Abstract

An application specific field programmable gate array ("ASFPGA") includes at least two fixed functional units in a single IC chip. Depending upon a specific application for the ASFPGA, the fixed functional units may include one or more bus interfaces, event timers, an interrupt controller, a Direct Memory Access ("DMA") controller, system timers, a real-time clock, a Random Access Memory ("RAM"), a clock synthesizer, a RAM Digital-to-Analog Converter ("DAC"), a display interface, a register file, a compressed image encoder/decoder ("CODEC"), or similar functional units. The ASFPGA also includes a general purpose field programmable gate array ("FPGA"). The FPGA is configurable to effect a specific digital logic circuit interconnection between fixed functional units. After the FPGA has been configured, the fixed functional units together with the FPGA perform all the functions specified for a particular ASIC design.

Claims

1. An application specific field programmable gate array ("ASFPGA") comprising:

at least two fixed functional units included in a single integrated circuit ("IC") chip; and

a general purpose field programmable gate array ("FPGA") also included in the IC chip, said FPGA interconnecting the fixed functional units, and being programmable to effect a specific digital logic circuit interconnection of the fixed functional units.

2. The ASFPGA of claim 1 wherein at least one of the fixed functional units is a bus interface.

3. The ASFPGA of claim 2 wherein the bus interface is an industry standard architecture ("ISA") bus interface.

4. The ASFPGA of claim 2 wherein the bus interface is an Peripheral Component Interconnect ("PCI") bus interface.

5. The ASFPGA of claim 4 wherein the ASFPGA includes a second bus interface.

6. The ASFPGA of claim 5 wherein the second bus interface is an ISA bus interface.

7. The ASFPGA of claim 1 wherein the ASFPGA is a System Logic Controller ("SLC").

8. The ASFPGA of claim 7 wherein the SLC includes interrupt controller fixed functional unit and a Direct Memory Access ("DMA") controller fixed functional unit that are all coupled to said FPGA.

9. The ASFPGA of claim 1 wherein the ASFPGA is a graphic controller.

10. The ASFPGA of claim 9 wherein the graphic controller includes Random Access Memory ("RAM") Digital-to-Analog Converter ("DAC") fixed functional unit and a display interface fixed functional unit that are all coupled to said FPGA.

11. The ASFPGA of claim 10 wherein the ASFPGA is a switching hub.

12. The ASFPGA of claim 11 wherein the switching hub is includes a switching-hub port fixed functional unit, a bus arbiter fixed functional unit;

and a content addressed memory ("CAM") fixed functional unit that are all coupled to said FPGA.