Merging data using a merge code from a look-up table and performing ECC generation on the merged data

• US 5,687,353 A
• Filed: 03/03/1995
• Issued: 11/11/1997
• Est. Priority Date: 03/03/1995
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: HAL Computer Systems, Inc. (Fujitsu Limited)
• Inventors: Chen, Chien, Lu, Yizhi
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US08/397,912
• Time in Patent Office: 984 Days
• Field of Search: 395/495, 395/482, 395/497.02, 395/182.03, 395/470, 395/182.04
• US Class Current: 711/155
• CPC Class Codes: G06F 11/1056 Updating check bits on partial write, i.e. read/modify/write
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories

Abstract

A system and method providing ECC protection for all data block sizes for which a computer system supports store (ST) accesses includes an access control logic unit which converts store accesses for small data block (≦64-bits) into read-modify (merge)-write accesses and a data merge logic unit which merges 64-bit data blocks retrieved by the load access with the small data block of the store access to create a new 64-bit data block. The data merge logic unit utilizes a merge code provided from a look-up table in a programmable logic array to perform the merging of the data blocks. An ECC generation logic unit processes the merged 64-bit data block, including the new small data block.

Claims

1. A cache memory system including ECC protection for all supported data store accesses, the system comprising:

a RAM core memory having control registers, an address input, a data input and a data output;

an access control logic unit having inputs for receiving load and store access signals and coupled to the control registers of the RAM core memory, for controlling access to the RAM core responsive to the received load and store access signals;

a programmable logic array having an input for receiving data store access information, an output, and including a look-up table for providing a merge code at the output responsive to the received data store access information;

a data merge logic unit having a first data input coupled to the data output of the RAM core memory, a second data input coupled to receive input data, a select input coupled to the output of the programmable logic array, and a data output, for combining data from the RAM core output with the received data at the second data input responsive to the merge code received from the programmable logic array; and

an ECC generation logic unit having a data input coupled to the data output of the data merge logic unit for receiving the data combined from the RAM core output and second data input, and a data output coupled to the data input of the RAM core memory unit, for performing standard ECC generation on the received combined data.

2. A method for handling ECC generation for all data block size store accesses supported in a memory system including a look-up table that has a selected data block size and an ECC generating process suited to the selected data block size, the method comprising the steps of:

receiving a store access request at a target address in the memory system for a data block having a size less than the selected data block size;

generating a load access request at the target address to retrieve a stored memory image at the target address having the selected data block size;

determining an appropriate merge code for the data block having a size less than the selected data block size from the look-up table;

combining, through the use of the merge code, the data block from the store access request with the retrieved data block having the selected data block size to form a new data block having the selected data block size; and

generating ECC for the new data block having the selected data block size using the ECC generation process suited to the selected data block size.