Selection from a plurality of bus operating speeds for a processor bus interface during processor reset
First Claim
1. A microprocessor comprising:
- an execution unit configured to execute a reset program upon receipt of a reset signal;
an in-circuit emulation (ICE) bus interface, said reset program causing said ICE bus interface to sample an ICE pin value;
a register file coupled to the execution unit, said reset program causing said ICE bus interface to store said sampled ICE pin value in a general register of said register file; and
a local bus interface having a bus speed configuration register corresponding to the register file, the execution unit reading general register in response to the reset program, said execution unit setting the bus speed configuration register of the local bus interface in response to the sampled ICE pin value, the bus speed configuration register controlling operating speed of the local bus interface after completion of execution of the reset program.
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Abstract
A method and apparatus for providing an interface from a processor to a bus. The interface is capable of operating at a speed selected from a plurality of speeds. An execution unit is coupled to a register file. The register file comprises a plurality of registers. Each of the registers of the register file is for storing data. The execution unit is for executing instructions. An instruction cache is coupled to the execution unit. The instruction cache and ROM is for storing instructions that can be used by the execution unit. A reset means is also coupled to the execution unit. Furthermore, a bus speed indication means is coupled to the execution unit and to the register files. The bus speed indication means is for receiving a bus speed indication signal. The bus speed indication signal is for indicating the selected operating speed for the bus interface. The reset signal is provided to the reset means and the bus speed indication signal is provided to the bus speed indication means. Upon receipt of the reset signal, the reset means causes a predetermined string of instructions to be retrieved from the instruction cache and to be executed by the execution unit. A first instruction of the predetermined string of instructions causes a value to be stored in a predetermined register of the register file. The value stored in the predetermined register of the register file is set according to the bus speed indication signal that was provided. A second instruction of the predetermined string of instructions, executed after the first instruction, provides the value stored in the predetermined register of the register file to the bus interface and thereby causes the bus interface to enter a mode wherein the bus interface operates at the selected speed specified by the bus speed indication signal.
35 Citations
17 Claims
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1. A microprocessor comprising:
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an execution unit configured to execute a reset program upon receipt of a reset signal; an in-circuit emulation (ICE) bus interface, said reset program causing said ICE bus interface to sample an ICE pin value; a register file coupled to the execution unit, said reset program causing said ICE bus interface to store said sampled ICE pin value in a general register of said register file; and a local bus interface having a bus speed configuration register corresponding to the register file, the execution unit reading general register in response to the reset program, said execution unit setting the bus speed configuration register of the local bus interface in response to the sampled ICE pin value, the bus speed configuration register controlling operating speed of the local bus interface after completion of execution of the reset program. - View Dependent Claims (2, 3)
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4. A method for setting operating speed of a local bus interface in a microprocessor having an execution unit, an in-circuit emulation (ICE) bus interface, a register file and the local bus interface, the method comprising the steps of:
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The execution unit executing a reset program upon receipt of a reset signal; The reset program causing the ICE bus interface to sample an ICE pin value; The reset program causing the ICE bus interface to store the sampled ICE pin value in a general register of the register file; The reset program causing the execution unit to read the general register; and The execution unit setting a bus speed configuration register of the local bus interface in response to sampled ICE pin value, the bus speed configuration register controlling the operating speed of the local bus interface after completion of the execution of the reset program. - View Dependent Claims (5, 6)
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7. A microprocessor comprising:
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execution means for executing a reset program in response to a reset signal; in-circuit emulation (ICE) means for providing an ICE bus interface, said reset program causing said ICE means to sample an ICE pin value; register means for storing data, said ICE means for storing said sampled ICE pin value in a general register of said register means in response to the reset program; and local bus interface means for providing a local bus interface, said local bus interface means having a bus speed configuration register of the register means corresponding thereto, said reset program causing said execution means to read said general register, said execution means setting a bus speed configuration register of said local bus interface means upon said sampled ICE pin value, said bus speed configuration register for controlling operating speed of said local bus interface means after completion of said reset program. - View Dependent Claims (8, 9)
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10. A computer system comprising:
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a microprocessor; a computer component; a bus, coupling said microprocessor to said computer component, said bus permitting transmission of data between said microprocessor and said computer component, said bus operating at a predetermined bus operating speed; a reset signal generator coupled to said microprocessor, said reset signal generator generating a reset signal; bus speed indication signal generator coupled to said microprocessor, said bus speed indication signal generator generating a bus speed indication signal during a predetermined time period when said reset signal is generated, said bus speed indication signal indicating said predetermined bus operating speed of said bus; said microprocessor having; an execution unit configured to execute a reset program in response to a reset signal; an in-circuit emulation (ICE) bus interface, said reset program causing said ICE bus interface to sample said bus speed indication signal as an ICE pin value; a register file coupled to the execution unit, said reset program causing said ICE bus interface to store said sampled ICE pin value in a general register of said register file; and a local bus interface having a bus speed configuration register of the register file corresponding thereto, said reset program causing said execution unit to read said general register, said execution unit setting a bus speed configuration register of said local bus interface based upon said sampled ICE pin value, said bus speed configuration register causing said local bus interface to operate at said predetermined bus operating speed after completion of execution of said reset program. - View Dependent Claims (11, 12)
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13. A microprocessor comprising:
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an execution unit configured to execute a reset program in response to a reset signal; a first bus interface, said execution unit executing a reset program upon receipt of a reset signal, said reset program causing said first bus interface to sample a first bus interface input value; a register file coupled to the execution unit, said reset program causing said first bus interface to store said sampled first bus interface input value in a general register of said register file; and a local bus interface having a bus speed configuration register of the register file corresponding thereto, said reset program causing said execution unit to read said general register, said execution unit configured to set the bus speed configuration register of said local bus interface in response to said sampled first bus interface input value, said bus speed configuration register controlling operating speed of said local bus interface after completion of execution of said reset program.
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14. A microprocessor comprising:
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execution means for executing a reset program in response to a reset signal; first bus means for providing a first bus interface, said ICE means to for sampling a first bus interface input value in response to the reset program; register means for storing data, said reset program causing said ICE means to store said sampled first bus interface input value in a general register of said register means; and local bus interface means for providing a local bus interface, said local bus interface means having a bus speed configuration register corresponding to the register means, said execution means configured to read said general register in response to said reset program, said execution means setting a bus speed configuration register of said local bus interface means in response to said sampled first bus interface input value, said bus speed configuration register controlling operating speed of said local bus interface means after completion of execution of said reset program.
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15. A method for setting operating speed of a local bus interface in a microprocessor having an execution unit, a first bus interface, a register file and said local bus interface, said method comprising the steps of:
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providing a reset signal to an execution unit; said execution unit executing a reset program upon receipt of the reset signal; said first bus interface sampling a first bus interface input value in response to execution of said reset program; said first bus interface storing said sampled first bus interface input value in a general register of said register file in response to said reset program; said execution unit reading said general register in response to execution of said reset program; and said execution unit setting a bus speed configuration register of said local bus interface in response to the sampled first bus interface input value, said bus speed configuration register controlling said operating speed of said local bus interface after completion of execution of said reset program.
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16. A computer system comprising:
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a microprocessor; a computer component; a bus, coupling said microprocessor to said computer component, said bus permitting transmission of data between said microprocessor and said computer component, said bus operating at a predetermined bus operating speed; a reset signal generator coupled to said microprocessor, said reset signal generator generating a reset signal; bus speed indication signal generator coupled to said microprocessor, said bus speed indication signal generator generating a bus speed indication signal during a predetermined time period when said reset signal is generated, said bus speed indication signal indicating said predetermined bus operating speed of said bus; said microprocessor having; an execution unit configured to execute a reset program in response to a reset signal; a first bus interface, said first bus interface sampling said bus speed indication signal as a first bus interface input value in response to said reset program; a register file, said first bus interface storing said sampled first bus interface input value in a general register of said register file in response to execution of said reset program; and a local bus interface having a bus speed configuration register of the register file corresponding thereto, said execution unit reading said general register in response to execution of said reset program, said execution unit setting a bus speed configuration register of said local bus interface according to said sampled first bus interface input value, said local bus interface to operating of said predetermined bus operating speed after completion of execution of said reset program.
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17. A microprocessor comprising:
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an execution unit capable of executing a reset program upon receipt of a reset signal; a register file coupled to the execution unit; an in-circuit emulation (ICE) bus interface configured to sample an ICE pin value in response to the reset program and to store the sampled ICE pin value in a general register of the register file; and a local bus interface having a bus speed configuration register corresponding to the register file, the execution unit being configured to read the general register in response to the reset program and to set the bus speed of the local bus interface according to the sampled ICE pin value, the local bus interface configured to continue at the operating speed according to the sampled ICE pin value after completion of the reset program.
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Specification