Device having automatic process for upgrading the performance of mobile systems

• US 5,687,398 A
• Filed: 10/20/1995
• Issued: 11/11/1997
• Est. Priority Date: 04/28/1993
• Status: Expired due to Term

• Current Assignee: Gemplus (Thales SA)
• Original Assignee: Gemplus International SA (Thales SA)
• Inventors: Martineau, Philippe
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Maung, Zarni
• Application Number:
  US08/546,274
• Time in Patent Office: 753 Days
• Field of Search: 235/382, 235/380, 235/441, 395/375, 395/275, 395/400, 395/899, 395/561
• US Class Current: 712/36
• CPC Class Codes: G06F 9/44 Arrangements for executing specific programs
• CPC Class Codes: G06F 9/445 Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/3552 Downloading or loading of personalisation data
• CPC Class Codes: G06Q 20/35765 Access rights to memory zones
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: H04M 17/00 Prepayment of wireline communication systems, wireless communication systems or telephone systems using a coded card to authorise calls from a telephone set H04M1/675
• CPC Class Codes: H04W 8/183 Processing at user equipment or user record carrier
• CPC Class Codes: H04W 8/245 from a network towards a terminal
• CPC Class Codes: H04W 88/02 Terminal devices
• CPC Class Codes: H04W 92/08 between user and terminal device
• CPC Class Codes: H04W 92/18 between terminal devices

Abstract

To simplify the manufacture of terminals for the use of chip cards, the system is designed so as to place a minimum set of instructions in these terminals and to transfer the storage of complementary instructions pertaining to uses of greater complexity and/or pertaining to the chip card into the chip card. To bring about the performance of these complementary instructions, an address designating an instruction of a complementary set is stored in a reserved memory of the chip card. The microprocessor of the chip card is furthermore provided with a microprogram enforcing the performance of an instruction thus designated as soon as it is detected that the reserved memory has been designated by an instruction of an elementary set of instructions of this microprocessor. It is shown that it is possible, in this way, to simplify and rationalize the manufacture of very powerful terminals.

Claims

1. A communications system comprising:

an electronic service center;

a communications interface, said communications interface being coupled to said electronic service center; and

a chip card, said chip card being coupled to said communications interface, said chip card comprising an electronic chip, said electronic chip including

a microprocessor,

a reserved memory zone, said reserved memory zone being coupled to said microprocessor, and

a program memory, said program memory being coupled to said reserved memory zone and to said microprocessor, said program memory including an automatic process said automatic process comprising an automatic process instruction, said automatic process instruction having data elements defining the characteristics of a supplementary instruction, and said automatic process defining means

for executing said automatic process instruction, wherein said execution of said automatic process instruction includes a writing of said characteristics of said supplementary instruction in said reserved memory zone of said chip card, and a designation of an address of said reserved memory zone,

for ascertaining that said automatic process instruction designates an address of said reserved memory zone, and

for automatically executing said supplementary instruction after said characteristics of said supplementary instruction have been written in said reserved memory zone, said automatic execution occurring contingent upon said ascertainment of said designation.

2. A system according to claim 1, wherein said automatic process further defines means for ascertaining the identity of said automatic process instruction as a member of an elementary set of automatic process instructions.

3. A system according to claim 1, wherein said address of said reserved memory zone stores a further address of said program memory at which said supplementary instruction is stored.

4. A system according to claim 1, wherein the automatic process further defines means for executing a complementary instruction from a complementary set of instructions whose address is stored in said reserved memory zone.

5. A system according to claim 1, wherein said reserved memory zone of said chip is non-volatile.

6. A system according to claim 1, wherein said reserved memory zone relates to a field for storing a sequential character of supplementary instructions, and wherein said automatic process further defines means for testing a value of said field.

8. A method according to claim 6, further comprising the step of ascertaining the identify of said automatic process instruction as a member of an elementary set of automatic process instructions.

7. A method comprising the steps of:

receiving at a communications interface an automatic process instruction, said automatic process instruction having data elements defining the characteristics of a supplementary instruction;

transmitting said automatic process instruction from said communications interface to a chip card;

processing said automatic process instruction in said chip card, said processing step including the steps of

executing said automatic process instruction, said executing step including the steps of

writing said characteristics of said supplementary instruction in a reserved memory zone of said chip card, and

designating an address of said reserved memory zone, ascertaining that said automatic process instruction designates an address of said reserved memory zone, and

automatically executing said supplementary instruction after said characteristics of said supplementary instruction have been written in said reserved memory zone, said automatic execution being contingent upon said ascertainment of said designation.

9. A method according to claim 7, wherein said address of said reserved memory zone stores a further address of said program memory at which said supplementary instruction is stored.

10. A method comprising the steps of:

receiving an instruction at a communications interface;

transmitting said instruction from said communications interface to a chip card;

processing said instruction in said chip card, said processing step including the steps of

executing said received instruction, said executing step including the step of writing data elements of said received instruction in a memory zone of said chip card, and

ascertaining whether said received instruction is an automatic process instruction, and if said received instruction is an automatic process instruction, then ascertaining whether said automatic process instruction designates an address of a reserved memory zone, and if said automatic process instruction designates an address of said reserved memory zone, then executing a supplementary instruction, said supplementary instruction having characteristics defined by said data elements of said automatic process instruction and being stored in said reserved memory zone.