ESD protection circuit

• US 5,689,133 A
• Filed: 09/09/1996
• Issued: 11/18/1997
• Est. Priority Date: 05/03/1993
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Broydo, Samuel, Li, Sheau-Suey, Duong, Khue, Ong, Randy T.
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US08/709,611
• Time in Patent Office: 435 Days
• Field of Search: 257/361, 257/205, 257/362, 257/363, 257/563
• US Class Current: 257/361
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements

Abstract

An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp. Certain P-type channel stop implants are positioned away from nearby N-regions to increase breakdown voltage.

Claims

1. A split bipolar transistor for an ESD protection circuit comprising

a plurality of adjacent collector regions, adjacent base regions, and adjacent emitter regions;

at least one collector region separated partly from an adjacent collector region by a Zener diode which extends in the direction of current flow, said Zener diode for reducing lateral current flow between adjacent collector regions to prevent current hogging in any one particular collector region during an ESD event, said Zener diode also for triggering snap-back action to dissipate high current to protect said split bipolar transistor during said ESD event.

2. A split bipolar transistor as in claim 1 in which said Zener diode stops short of a region in which collector contacts are positioned.

3. A split bipolar transistor as in claim 1 in which at least one collector region is separated at least partly from an adjacent collector region by an oxide region which extends in the direction of current flow.

4. A split bipolar transistor as in claim 1 in which said collector regions are separated from adjacent collector regions by alternate Zener diodes and oxide regions.

5. A split bipolar transistor comprising:

(a) a plurality of adjacent collector regions;

(b) a plurality of adjacent base regions;

(c) a plurality of adjacent emitter regions, said plurality of adjacent emitter regions and said plurality of adjacent collector regions separated by respective field oxide dividers, wherein each respective collector, base and emitter region further comprises;

(c1) a collector contact which contacts said collector region;

(c2) an emitter contact which contacts said emitter region; and

(c3) a base contact;

wherein said base region is formed in a well in which said collector region and emitter region are positioned, said base region being between said collector region and said emitter region; and

wherein said base contact is positioned on an opposite side of said emitter region from said base region, at a given distance away from said base region, wherein said given distance is at least twice as far from said base region as said emitter contact is positioned away from said base region, wherein said given distance through said well provides (1) a base resistor electrically in series with said base region and said base contact and (2) protection for said base contact from high energy dissipation through a base region-collector region junction during an ESD event.

6. A bipolar transistor as described in claim 5 wherein said base resistor is for increasing voltage at said base region during an ESD event in order to turn on said bipolar transistor to dissipate current.

7. A bipolar transistor as described in claim 6 wherein said base contact comprises a base contact metal coupled to a salicide region that is disposed over said well at said given distance from said base region.

8. A split bipolar transistor for an ESD protection circuit comprising:

a plurality of adjacent collector regions, adjacent base regions, and adjacent emitter regions;

each collector region separated at least partly from an adjacent collector region by a divider which reduces lateral current flow between adjacent collector regions during an ESD event to prevent current hogging in any particular collector region;

said collector regions being formed of N-type conductivity material, said divider being formed along part of its length by oxide, and along that part of its length next to said base by lightly doped N-region which extends beneath a field oxide region above a base of said transistor, said lightly doped N-region joining said field oxide in a region where said field oxide region is approximately straight, said lightly doped N-region for providing a gradual change in electron density at corners of said field oxide to provide minimum tendency toward breakdown during programming.