Four-terminal power MOSFET switch having reduced threshold voltage and on-resistance

• US 5,689,144 A
• Filed: 05/15/1996
• Issued: 11/18/1997
• Est. Priority Date: 05/15/1996
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Williams, Richard K.
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): PALADINI, ALBERT WILLIAM
• Application Number:
  US08/649,747
• Time in Patent Office: 552 Days
• Field of Search: 307/130, 307/116, 327/389, 327/434, 327/534, 327/565, 327/566, 327/536, 327/537, 257/58, 257/341, 257/401, 326/68, 326/97, 326/98, 326/114, 437/913
• US Class Current: 307/130
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

The threshold voltage and on-resistance of a four-terminal power MOSFET switch are reduced by partially forward-biasing (to, for example, 0.5 V) the junction between the body and electrical source of the MOSFET. Preferably, as the MOSFET is switched on and off to control the current to a load, the body is switched synchronously with the gate so that the source-body junction is partially forward-biased (i.e., biased at a level that is insufficient to cause a forward current to flow through the junction) when the MOSFET switch is turned on and the body is shorted to the source when the MOSFET switch is turned off, thereby reducing the leakage current through the MOSFET in its off state. The body bias may be derived directly from the gate voltage or from a separate voltage supply line. A current-limiting device and a voltage clamp may be used to limit the body current and voltage, respectively.

Claims

1. A method of switching a current on and off comprising the steps of:

providing a MOSFET, the MOSFET comprising first and second regions of a first conductivity type formed in a semiconductor substrate and separated by a body region of a second conductivity type, and a gate separated from channel region within the body region by a dielectric layer, neither of the first and second regions being shorted to the body region;

applying a voltage V_DS across the first and second regions;

applying a voltage V_G (on) to the gate so as to cause a current to flow between the first and second regions through the channel region;

applying a voltage V_B to the body region so as to forward-bias a PN junction between the body region and the second region, the voltage V_G being set at a level such that a resulting forward-bias across the PN junction is not sufficient to cause a substantial current to flow across the PN junction;

applying a voltage V_G (off) to the gate so as to terminate the flow of current between the first and second regions through the channel region; and

removing the voltage V_B from the body region.

2. The method of claim 1, wherein the step of applying the voltage V_G (on) to the gate and the step of applying the voltage V_B to the body region are performed simultaneously.

3. The method of claim 2, wherein the step of applying the voltage V_G (off) to the gate and the step of removing the voltage V_B from the body region are performed simultaneously.

4. The method of claim 1 wherein the step of applying the voltage V_G (off) to the gate and the step of removing the voltage V_B from the body region are performed simultaneously.

5. A power MOSFET switch for switching a current to a load, the power MOSFET switch comprising:

a four-terminal MOSFET having first, second gate and body terminals, no one of the terminals being shorted to any of the other terminals;

a first switch connected between the first and gate terminals;

a second switch connected between the first and body terminals;

wherein the first and second switches are ganged together, the first switch passing a voltage V_G (on) to the gate terminal and the second switch passing a voltage V_B to the body terminal when the first and second switches are in a first position, the first switch passing a voltage V_G (off) to the gate terminal and the second switch removing the voltage V_B from the body terminal when the first and second switches are in a second position.

6. The power MOSFET switch of claim 5 wherein each of the first and second switches comprises a single-pole, double-throw switch, the first switch having a common terminal connected to the gate terminal, a first terminal connected to the voltage V_G and a second terminal connected to the first terminal of the MOSFET, the second switch having a common terminal connected to the body terminal, a first terminal connected to the voltage V_B and a second terminal connected to the first terminal of the MOSFET.

7. A power MOSFET switch arrangement comprising:

a four-terminal power MOSFET having source, drain, gate and body terminals, no one of the terminals being shorted to any of the other terminals; and

a resistor connected between the gate and body terminals.

8. The power MOSFET switch arrangement of claim 7 further comprising a voltage clamping device connected between the body and source terminals.

9. The power MOSFET switch arrangement of claim 8 wherein the voltage clamping device comprises a diode.

10. The power MOSFET switch arrangement of claim 9 wherein the diode is a Schottky diode.

11. The power MOSFET switch arrangement of claim 8 wherein the voltage clamping device comprises a second MOSFET, the second MOSFET having source, gate and body terminals shorted to the body terminal of the power MOSFET and a drain terminal connected to the source terminal of the power MOSFET.

12. A power MOSFET switch arrangement comprising:

a four-terminal power MOSFET having source, drain, gate and body terminals, no one of the terminals being shorted to any of the other terminals; and

a depletion-mode MOSFET connected between the gate and body terminals, the depletion-mode MOSFET having source, body and gate terminals shorted together.

13. The power MOSFET switch arrangement of claim 12 further comprising a voltage clamping device connected between the body and source terminals.

14. The power MOSFET switch arrangement of claim 13 wherein the voltage clamping device comprises a diode.

15. The power MOSFET switch arrangement of claim 14 wherein the diode is a Schottky diode.

16. The power MOSFET switch arrangement of claim 13 wherein the voltage clamping device comprises a second MOSFET, the second MOSFET having source, gate and body terminals shorted to the body terminal of the power MOSFET and a drain terminal connected to the source terminal of the power MOSFET.

17. A power MOSFET switch arrangement comprising:

a four-terminal power MOSFET having source, drain, gate and body terminals, no one of the terminals being shorted to any of the other terminals;

a resistor connected between the gate and body terminals; and

a depletion-mode MOSFET connected between the source and body of the power MOSFET, the depletion-mode MOSFET having source and body terminals shorted together and a gate terminal connected to the gate of the power MOSFET.

18. The power MOSFET switch arrangement of claim 17 further comprising a voltage clamping device connected between the body and source terminals.

19. The power MOSFET switch arrangement of claim 18 wherein the voltage clamping device comprises a second MOSFET, the second MOSFET having source, gate and body terminals shorted to the body terminal of the power MOSFET and a drain terminal connected to the source terminal of the power MOSFET.

20. The power MOSFET switch arrangement of claim 17 further comprising a second depletion-mode MOSFET connected between the gate and body terminals of the power MOSFET, the depletion-mode MOSFET having source, body and gate terminals shorted together.

21. A power MOSFET switch arrangement comprising:

a power MOSFET having source, drain, gate and body terminals, no one of the terminals being shorted to any of the other terminals;

a voltage supply line;

a first inverter having an output terminal connected to the gate terminal and a power input terminal connected to the voltage supply line; and

a second inverter having an output terminal connected to the body terminal and a power input terminal connected through a resistor to the voltage supply line.

22. The power MOSFET switch arrangement of claim 21 further comprising a voltage clamping device connected between the body and source terminals.

23. The power MOSFET switch arrangement of claim 22 wherein the voltage clamping device comprises a second MOSFET, the second MOSFET having source, gate and body terminals shorted to the body terminal of the power MOSFET and a drain terminal connected to the source terminal of the power MOSFET.

24. A power MOSFET switch arrangement comprising:

a power MOSFET having source, drain, gate and body terminals, no one of the terminals being shorted to any of the other terminals;

a voltage supply line;

a first inverter having an output terminal connected to the gate terminal and a power input terminal connected to the voltage supply line;

a second inverter having an output terminal connected to an input terminal of the first inverter and a power input terminal connected to the voltage supply line; and

third and fourth MOSFETs connected in series between the voltage supply line and ground, a common node between the third and fourth MOSFETs being connected to the body terminal of the power MOSFET, the output terminal of the first inverter being connected to the gate of the third MOSFET and the output terminal of the second inverter being connected to the gate of the fourth MOSFET.

25. The power MOSFET switch arrangement of claim 24 further comprising a voltage clamping device connected between the body and source terminals of the power MOSFET.

26. A power MOSFET switch arrangement comprising:

a power MOSFET having source, drain, gate and body terminals, no one of the terminals being shorted to any of the other terminals;

a voltage supply line;

a first inverter having an output terminal connected to the gate terminal and a power input terminal connected to the voltage supply line;

a second inverter having an output terminal connected to the body terminal; and

a voltage divider connected to the voltage supply line, a midpoint of the voltage divider being connected to a power input terminal of the second inverter.

27. The power MOSFET switch arrangement of claim 26 wherein the voltage divider comprises second and third MOSFETs, each of said second and third MOSFETs having source, body and gate terminals shorted together.

28. A power MOSFET switch arrangement comprising:

a power MOSFET having source, drain, gate and body terminals, no one of the terminals being shorted to any of the other terminals;

a voltage supply line;

a first inverter having an output terminal connected to the gate terminal and a power input terminal connected to the voltage supply line;

a second inverter having an output terminal connected to the body terminal; and

a linear regulator connected to the voltage supply line, an output terminal of the linear regulator being connected to a power input terminal of the second inverter.