Proportional DC power control system and method

• US 5,689,411 A
• Filed: 12/06/1996
• Issued: 11/18/1997
• Est. Priority Date: 06/03/1994
• Status: Expired due to Fees

• Current Assignee: Kenneth Michael Chabraya
• Original Assignee: Kenneth Michael Chabraya
• Inventors: Chabraya, Kenneth Michael
• Primary Examiner(s): Ro, Bentsu
• Application Number:
  US08/761,393
• Time in Patent Office: 347 Days
• Field of Search: 323/205, 323/207, 323/212, 323/217, 323/234, 323/237, 323/265, 323/355, 323/359, 363/13, 363/74, 363/78, 363/123, 363/125, 363/128, 363/129, 363/130, 318/440, 318/441, 318/442, 318/471, 219/200, 219/209, 219/221, 219/482, 219/488, 219/490, 219/494, 219/497, 219/507, 219/509, 219/510, 219/511, 219/512, 219/520, 219/538
• US Class Current: 363/74
• CPC Class Codes: H02M 5/2573 with control circuit
• CPC Class Codes: H02M 7/217 using semiconductor devices only

Abstract

A control circuit is disclosed which uses AC power input and provides DC power output which is not limited by DC semiconductor switch power dissipation capabilities. Switching is performed on the AC signal to provide time proportional AC power which is then transformed and rectified to provide relatively high proportional or adjustable power to a DC load without electrical noise. The DC load is monitored for a controlled characteristic, such as temperature, and a monitor signal is provided to a control for controlling the time proportional AC power output, in accordance with the DC load demand. A dimensionally stable temperature controlled semiconductor test chuck is described presenting a DC heater load for the control circuit.

Claims

1. A control system for low electrical noise semiconductor testing at predetermined temperature using an AC power supply, comprising

AC switching means controllable between and "off" nonconducting state and an "on" conducting state, said switching means being connected to the AC power supply and providing a time proportional AC power output during said "on" conducting state,

rectifying means connected to receive said time proportional AC power output and providing DC power output,

at least at 300 watt DC heater connected to receive said DC power output,

semiconductor test mounting chuck having a semiconductor mounting surface thereon and being thermally connected to said DC heater,

temperature sensing means positioned proximate to said semiconductor mounting surface for providing a temperature indicative output signal,

control means for receiving said temperature indicative output signal and providing a control signal output, and

switch control means within said AC switching means for receiving said control signal output and controlling said time proportional AC power output to provide the predetermined temperature at said semiconductor mounting surface.

2. A control system as in claim 1 wherein said semiconductor test mounting chuck comprises

a top plate having said semiconductor mounting surface on the upper surface thereof and having a lower surface,

a depending skirt on the periphery of said top plate,

a semiconductor wafer having an upper surface abutting said top plate lower surface and having a lower wafer surface,

said 300 watt DC heater comprising a heater blanket abutting said lower wafer surface,

bottom clamping means for holding said top plate, semiconductor wafer and heater blanket in sandwiched relation, and

thermal reflection means interposed between said heater blanket and said bottom clamping means, whereby heat is directed toward and electrical isolation is provided for said semiconductor mounting surface.

3. A control system as in claim 2 wherein said bottom clamping means comprises,

a plurality of high dielectric low temperature coefficient standoffs connected to said top plate and extending therewithin to a position proximate to said semiconductor mounting surface,

a bottom clamping plate abutting said thermal reflection means,

a base mounting flange,

spacer means between said bottom clamping plate and said base mounting flange, whereby an air gap is created therebetween,

said semiconductor wafer, heater blanket, thermal reflection means, and bottom clamping plate having a plurality of aligned openings therein for allowing said plurality of standoffs to pass therethrough, and

fastening means for engaging said plurality of standoffs and said base mounting flange, whereby said semiconductor test mounting chuck is secured together.

4. A temperature controllable low electrical noise DC power heated semiconductor test chuck, comprising

a top plate having an exterior semiconductor mounting surface and an opposing interior surface,

a depending skirt on said top plate surrounding said opposing interior surface,

a dielectric wafer having an upper surface abutting said top plate interior surface and a lower wafer surface,

a DC heater blanket abutting said lower wafer surface on one side and having a lower heater blanket side,

heat reflecting means in contact with said DC heater blanket on said lower heater blanket side,

bottom clamping and chuck mounting means adjacent said heat reflecting means on the side thereof remote from said DC heater blanket contact, whereby heat from said DC heater blanket is directed toward said semiconductor mounting surface and away from said bottom clamping and chuck mounting means, and whereby said semiconductor mounting surface is electrically isolated from said DC heater blanket, is maintained substantially flat over operating temperature range, and is substantially free of radiated electrical noise.

5. A semiconductor test chuck as in claim 4 wherein said dielectric wafer comprises a semiconductor wafer.

6. A semiconductor test chuck as in claim 4 wherein said dielectric wafer comprises a silicon wafer and a diamond layer on said silicon wafer.

7. A semiconductor test chuck as in claim 4 wherein said heat reflecting means comprises flame thermal paper.

8. A semiconductor test chuck as in claim 4, comprising

a plurality of high dielectric low temperature coefficient standoffs connected to said top plate and extending therethrough to a position proximate to said exterior semiconductor mounting surface, and

means for connecting said bottom clamping and chuck mounting means to said plurality of standoffs, said dielectric wafer, DC heater blanket and heat reflecting means having a plurality of aligned openings therein for allowing said plurality of standoffs to pass therethrough.

9. A semiconductor test chuck as in claim 4 wherein said DC heater blanket comprises at least a 300 watt heater.

10. A semiconductor test chuck as in claim 4 comprising temperature sensing means positioned proximate to said exterior semiconductor mounting surface.

11. A method for controlling temperature level and reducing radiated electrical noise levels during semiconductor component testing, wherein AC power is supplied, comprising the steps of

switching the AC power to provide time proportional AC power output to obtain time proportional DC power output,

providing at least 300 watts of the DC power output to a DC heater,

thermally connecting said DC heater to a semiconductor component mounting surface,

continuously sensing the temperature of the semiconductor component mounting surface,

providing a temperature indicative output signal from the continuous sensing, and

continuously controlling the time proportional AC power output to provide a predetermined temperature level at the semiconductor mounting surface.

12. The method of claim 11 wherein the semiconductor mounting surface and the DC heater are arrayed in layered relationship with an underlying support structure, further comprising the steps of

interposing a thermal reflecting layer between the underlying support structure and the DC heater.

13. The method claim 12 further comprising the steps of

extending a plurality of high dielectric low temperature coefficient members from attached at one end to a position adjacent the semiconductor component mounting surface through the layered DC heater and thermal reflecting layer, and

attaching the other end of the plurality of high dielectric low temperature coefficient members to the underlying support structure.