Method and apparatus for compacting integrated circuits with wire length minimization

• US 5,689,433 A
• Filed: 11/28/1995
• Issued: 11/18/1997
• Est. Priority Date: 11/19/1992
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Edwards, Lawrence B.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/433,438
• Time in Patent Office: 721 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/112
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A computer-aided design method and apparatus for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a specified circuit layout into a set of trapezoids and storing the resulting cells in a database identifying the boundaries of each cell, and the cell adjacent each boundary. The method additionally includes a procedure for minimizing wire lengths in the compacted layout. Nonempty cells are identified as being of specific materials, and empty spaces between cells are represented. For each cell boundary, the database also stores data representing the boundary edge'"'"'s end points. Neighboring cells on the same and related layers of the circuit layout share edges in the database. When a point on an edge of a cell is moved, the edge of each neighboring cell that shares that point is also moved. To adjust a circuit layout, the cells in the layout are processed in a sorted order. For each cell, width and spacing design rules are applied to first and second edges of the cell, which may result in movement of the cell and/or adjustment of the cell'"'"'s width. An adjacent cell adjustment process conforms cells shared points with the adjusted cell. Once the compaction procedure is carried out in a positive x-direction, the coordinates are reversed and it is carried out again in a second pass. The compaction method is performed once for x-direction compaction and once for y-direction compaction. The compaction process is computationally efficient because each cell is linked by the database to its adjacent cells, virtually eliminating the need to search through cells not needed for each design rule check, and because movement of one cell'"'"'s edges automatically adjusts adjacent cells via their shared edges. The wire minimization embodiment of the invention includes determining whether the second edges have been moved in the second pass, and if so applying the width rules to the first edges to minimize the length of wire represented by the width of the cell having the adjusted edges.

Claims

1. A computer-aided design system for revising a multilayer integrated circuit layout, comprising:

data receiving means for receiving data representing said integrated circuit layout;

a design rule dictionary representing a set of design rules, a first subset of said design rules involving spacing design rules and a second subset of said design rules including width design rules;

a circuit layout database including;

a cell table representing cells, each cell representing a region of an identified layer of said integrated circuit layout, said cell table including cells representing all empty spaces between non-empty regions of each layer of said integrated circuit layout;

edge data representing all edges of all said cells in said cell table, said edge data including point data representing each edge'"'"'s endpoints such that each point which is an edge endpoint of two or more edges is represented by a single, shared point datum;

each said point datum representing a point location and a move value indicating movement of an edge'"'"'s endpoint;

adjacent cell data indicating adjacent cell data indicating, for each edge of each cell, which other cell is adjacent said cell at said edge;

circuit layout compaction mechanism, said mechanism including;

a circuit layout compaction procedure for adjusting, in accordance with said design rules represented by said design rule dictionary, said point data in said database so as to adjust said cells'"'"' positions and sizes;

wherein each adjustment of said point data for one edge of one cell automatically adjusts a corresponding edge of said other cell adjacent to said one edge by way of their shared point data in said database;

a wire length minimization procedure for minimizing a width of each non-empty cell whose width is not minimal and that meets a predefined criteria;

wherein said wire length minimization procedure readjusts said point data for more than one edge of a selected cell and for those edges adjacent to each readjusted edge; and

revised circuit layout generation mechanism for generating a revised circuit layout in accordance with said adjusted point data in said database.

2. The system of claim 1,

said wire length minimization procedure including:

a cell selection means for selecting cells from said database to process in a specified sequence, and for identifying each selected cell'"'"'s top and bottom edges;

a first bottom edge position mechanism for determining a position for each bottom edge of a selected cell;

a top edge position mechanism for determining a position for each top edge of a selected cell, said top edge position mechanism positioning a top edge relative to said cell'"'"'s bottom edge and in accordance with said width rules;

a second bottom edge position mechanism for determining a position of a bottom edge associated with a cell that is located in front of a selected cell, said position made in accordance with said width rules; and

an adjacent edge position mechanism for determining positions for select edges of adjacent cells to a selected cell.

3. The system of claim 2,

said first bottom edge position mechanism including:

a first position determination mechanism for positioning said bottom edge in a same position as determined by said circuit layout compaction procedure; and

a second position determination mechanism for positioning said bottom edge in a different position from a position determined by said circuit layout compaction procedure if said cell'"'"'s associated top edge has been positioned by said adjacent edge position mechanism, said associated top edge is adjacent only to empty cells, and application of said width design rules results in a smaller width for said selected cell.

4. A computer readable storage medium for storing data for access by programs being executed on a data processing system including at least one server computer and a plurality of client computers, said medium comprising:

data receiving means for receiving data representing said integrated circuit layout;

a design rule dictionary representing a set of design rules, a first subset of said design rules involving spacing design rules and a second subset of said design rules including width design rules;

a circuit layout database including;

a cell table representing cells, each cell representing a region of an identified layer of said integrated circuit layout, said cell table including cells representing all empty spaces between non-empty regions of each layer of said integrated circuit layout;

edge data representing all edges of all said cells in said cell table, said edge data including point data representing each edge'"'"'s endpoints such that each point which is an edge endpoint of two or more edges is represented by a single, shared point datum;

each said point datum representing a point location and a move value indicating movement of an edge'"'"'s endpoint;

adjacent cell data indicating adjacent cell data indicating, for each edge of each cell, which other cell is adjacent said cell at said edge;

circuit layout compaction mechanism, said mechanism including;

a circuit layout compaction procedure for adjusting, in accordance with said design rules represented by said design rule dictionary, said point data in said database so as to adjust said cells'"'"' positions and sizes;

wherein each adjustment of said point data for one edge of one cell automatically adjusts a corresponding edge of said other cell adjacent to said one edge by way of their shared point data in said database;

a wire length minimization procedure for minimizing a width of each non-empty cell whose width is not minimal and that meets a predefined threshold criteria;

wherein said wire length minimization procedure readjusts said point data for more than one edge of a selected cell and for those edges adjacent to each readjusted edge; and

revised circuit layout generation mechanism for generating a revised circuit layout in accordance with said adjusted point data in said database.

5. The medium of claim 4,

said wire length minimization procedure including:

a cell selection means for selecting cells from said database to process in a specified sequence, and for identifying each selected cell'"'"'s top and bottom edges;

a first bottom edge position mechanism for determining a position for each bottom edge of a selected cell;

a top edge position mechanism for determining a position for each top edge of a selected cell, said top edge position mechanism positioning a top edge relative to said cell'"'"'s bottom edge and in accordance with said width rules;

a second bottom edge position mechanism for determining a position of a bottom edge associated with a cell that is located in front of a selected cell, said position made in accordance with said width rules; and

an adjacent edge position mechanism for determining positions for select edges of adjacent cells to a selected cell.

6. The medium of claim 5,

said first bottom edge position mechanism including:

a first position determination mechanism for positioning said bottom edge in a same position as determined by said circuit layout compaction procedure; and

a second position determination mechanism for positioning said bottom edge in a different position from a position determined by said circuit layout compaction procedure if said cell'"'"'s associated top edge has been positioned by said adjacent edge position mechanism, said associated top edge is adjacent to only empty cells, and application of said width design rules results in a smaller width for said selected cell.

7. A method for compacting an integrated circuit layout in accordance with a specified set of spacing design rules and width design rules, the method being executed by a processor having a memory and controlled by a program stored in the memory and including the steps of:

(1) selecting a first coordinate direction;

(2) storing in said memory a connectivity data structure representing the integrated circuit layout as a set of cells, each said cell being defined as being of a given material or as empty, the data structure including data representing points defining edges and boundaries of said cells;

(3) designating each edge of each cell in having a lower value in the selected coordinate direction as a bottom edge, and designating each edge of each cell having a higher value in the selected coordinate direction as a top edge;

(4) ordering the cells into an sorted cell list in accordance with the first coordinate direction;

(5) assigning to each point of the layout an offset reposition that point at the least-valued location of the layout in the selected coordinate direction;

(6) for each cell of the sorted cell list, selecting that cell as the current cell, and;

for each point on the top edge of the current cell, assigning each point on the top edge the maximum move distance for any points on the top edge;

for each bottom edge of the current cell, applying the spacing design rules to position edges of other cells a minimum allowable distance from an edge of the current cell, and applying the width design rules to position top and bottom edges of the current cell a minimum allowable width from one another;

for each top edge of the current cell, applying the width design rules to position top and bottom edges of the current cell a minimum allowable width from one another, and applying the spacing design rules to position edges of other cells a minimum allowable distance from an edge of the current cell;

(7) recursively adjusting edges of cells sharing points with edges having at least one point that was moved in step 6 to move edges that share points the same distance;

(8) propagating the moves of top edges that were moved in step 6 to other edges having higher-valued positions in the input layout, according to the first coordinate direction, for positioning said other edges the minimum allowable spacing distance from said top edges moved in step 6;

(9) using the move assignments of said top edges to calculate further move assignments for said bottom edges, to maximize the compaction effect on the integrated circuit layout;

(10) reversing the values of the positions of objects in the first coordinate direction such that said top edges are redefined as new bottom edges and said bottom edges are defined as new top edges; and

(11) using the move assignments of the former bottom edges (new top edges) as adjusted in step 9 to calculate further move assignments for the former top edges (new bottom edges) to maximize the compaction effect on the integrated circuit layout.

8. The method of claim 7, wherein step 9 includes the steps of:

reversing the values of the positions of objects in the first coordinate direction such that the former top edges are redefined as new bottom edges and the former bottom edges are defined as new top edges;

repeating step 6 using the reversed coordinate values to maximize the compaction effect on the integrated circuit layout.

9. The method of claim 7, further including carrying out steps 1-7 in a second coordinate direction.

10. The method of claim 7, including, after step 1 and before step 2, the step of fracturing the cells in the first coordinate direction as necessary to ensure that all stored cells are convex.

11. The method of claim 7, wherein step 9 further includes the step of using the move assignments of said bottom edges as adjusted in step 9 to calculate further move assignments for said top edges.

12. A method for revising an integrated circuit layout in accordance with a specified set of spacing design rules and width design rules, the method being executed by a processor having a memory and controlled by a program stored in the memory and including the steps of:

(1) selecting a first coordinate direction;

(2) storing in said memory a connectivity data structure representing the integrated circuit layout as a set of cells, each said cell being defined as being of a given material or as empty, the data structure including data representing points defining edges and boundaries of said cells;

(3) designating each edge of each cell having a lower value in the selected coordinate direction as a bottom edge, and designating each edge of each cell having a higher value in the selected coordinate direction as a top edge;

(4) ordering the cells into an sorted cell list in accordance with the selected coordinate direction;

(5) for each cell of the sorted cell list, selecting that cell as the current cell, and;

applying said spacing and width design rules to each top and bottom edge of said current cell, said application adjusting said edge'"'"'s position and size; and

recursively adjusting edges of adjacent cells affected by the application of said design rules to said current cell;

(6) designating each edge of each cell having a lower value in the selected coordinate direction as a top edge, and designating each edge of each cell having a higher value in the selected coordinate direction as a bottom edge;

(7) for each cell of the sorted cell list, selecting that cell as the current cell, and;

(i) determining a position for a bottom edge of said current cell;

(ii) applying said width design rules to a top edge of said current cell in order to position said top edge within a minimum width distance from said bottom edge;

(iii) positioning bottom edges associated with each cell located in front of said current cell in accordance with said width design rules; and

(iv) adjusting select edges of adjacent cells to said current cell.

13. The method of claim 12,

(8) designating each edge of each cell having a lower value in the selected coordinate direction as a bottom edge, and designating each edge of each cell having a higher value in the selected coordinate direction as a top edge;

(9) selecting a second coordinate direction; and

(10) repeating steps (2)-(7) for the second coordinate direction.

14. The method of claim 12,

said step (7)(i) further comprising the steps of:

(a) determining if a top edge of said current cell was adjusted in step (7);

(b) if said top edge was adjusted in step (7), calculating a position for said bottom edge such that said bottom edge satisfies said width design rules; and

(c) if said top edge was not adjusted in step (7), utilizing as a position for said bottom edge said adjusted position determined previously in step (5).

15. The method of claim 14,

said 7(i)(b) further comprising the step of:

(1) performing said calculation step if said top edge is adjacent only to empty cells and application of said width design rules result in a smaller width for said cell.