Semiconductor non-volatile ferroelectric memory transistor accompanied with capacitor for increasing potential difference applied to ferroelectric layer
First Claim
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1. A semiconductor non-volatile ferroelectric memory cell fabricated on a semiconductor substrate, comprising:
- a memory transistor including source and drain regions formed on both sides of a channel region, a lower gate insulating layer formed of paraelectric material on said channel region, a lower gate electrode laminated on said lower gate insulating layer, an upper gate insulating layer formed of ferroelectric material on said lower gate electrode and an upper gate electrode formed on said upper gate insulating layer, and storing a data bit in the form of remanence in said upper gate insulating layer; and
a paraelectric capacitor including a lower electrode electrically connected to said channel region, an insulating layer formed of paraelectric material on said lower electrode and an upper electrode electrically connected to said lower gate electrode of said memory transistor.
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Abstract
A semiconductor non-volatile ferroelectric memory transistor has a lower paraelectric capacitor for creating a conductive channel between a source region and a drain region and an upper ferroelectric capacitor stacked on the lower paraelectric capacitor for storing a data bit in the form of remanence in a ferroelectric layer, and a paraelectric capacitor is connected between the channel region and the upper electrode of the lower paraelectric capacitor so as to increase a potential difference applied across the ferroelectric layer, thereby improving information storing characteristics.
32 Citations
8 Claims
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1. A semiconductor non-volatile ferroelectric memory cell fabricated on a semiconductor substrate, comprising:
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a memory transistor including source and drain regions formed on both sides of a channel region, a lower gate insulating layer formed of paraelectric material on said channel region, a lower gate electrode laminated on said lower gate insulating layer, an upper gate insulating layer formed of ferroelectric material on said lower gate electrode and an upper gate electrode formed on said upper gate insulating layer, and storing a data bit in the form of remanence in said upper gate insulating layer; and a paraelectric capacitor including a lower electrode electrically connected to said channel region, an insulating layer formed of paraelectric material on said lower electrode and an upper electrode electrically connected to said lower gate electrode of said memory transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor non-volatile ferroelectric memory cell comprising:
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a field effect transistor fabricated on a semiconductor substrate; a ferroelectric capacitor having a first electrode and a second electrode connected to a gate electrode of said field effect transistor; and a paraelectric capacitor having a third electrode connected to said semiconductor substrate and a fourth electrode connected to said gate electrode of said field effect transistor so as to be coupled in parallel to a gate insulating capacitor of said field effect transistor.
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Specification