Semiconductor memory device and method for driving the same

• US 5,689,468 A
• Filed: 12/13/1995
• Issued: 11/18/1997
• Est. Priority Date: 12/21/1994
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Ihara, Makoto
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US08/571,544
• Time in Patent Office: 706 Days
• Field of Search: 365/203, 365/203.03, 365/149
• US Class Current: 365/203
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A semiconductor memory device includes at least one memory block comprising: a plurality of word lines; a plurality of bit lines; and a plurality of memory cells each including a first switching element and a capacitor which is connected to the bit line via the first switching element, a node comprising a capacitance member having a predetermined capacitance, a second switching element for connecting the bit line to the node, a bit line precharge circuit, a capacitance member precharge circuit, and a control circuit for controlling the first switching element so as to connect electrically the memory cell which is coupled to the selected word line of a read operation to the corresponding bit line, and for controlling the second switching element so as to connect electrically the selected bit line of the read operation to the node comprising the precharged capacitance member, whereby changing the electric potential of the selected bit line so as to apply a predetermined voltage signal to the capacitor of the selected memory cell, whereby reading a data stored in the capacitor of the selected memory cell onto the selected bit line and the node.

Claims

1. A semiconductor memory device including at least one memory block comprising:

a plurality of word lines;

a plurality of bit lines; and

a plurality of memory cells which are disposed at crossings of the word lines and the bit lines, each memory cell including first switching means and a capacitor which is connected to the bit line via the first switching means, the first switching means being turned on and off in accordance with a signal level supplied from the corresponding word line, and data being written to and read from the capacitor by a voltage signal supplied from the bit line,

wherein the semiconductor memory devices includes;

a node comprising capacitance means having a predetermined capacitance;

second switching means for connecting the bit line to the node;

means for precharging the plurality of bit lines to a first voltage potential;

means for precharging the capacitance means to a second voltage potential, wherein the first and second voltage potential are not equal to one another; and

control means for controlling the first switching means so as to connect electrically the memory cell which is coupled to the word line selected in a read operation to the corresponding bit line, and for controlling the second switching means so as to connect electrically the bit line which is selected in the read operation to the node comprising the precharged capacitance means, wherein the electric potential of the selected bit line changes to a third voltage potential which is between the first and second voltage potentials so as to apply the voltage potential to the capacitor of the selected memory cell which is coupled to the selected word line and the selected bit line, thereby reading a data signal corresponding the data stored in the capacitor of the selected memory cell onto the selected bit line and the node.

2. A semiconductor memory device according to claim 1, wherein the node comprising the capacitance means is provided for each of the plurality of bit lines, and the second switching means connects the bit line which is selected from the plurality of bit lines to the corresponding node.

3. A semiconductor memory device according to claim 1, wherein the node comprising the capacitance means is provided commonly for the plurality of bit lines, and the second switching means connects the bit line which is selected from the plurality of bit lines to the node.

4. A semiconductor memory device including at least one memory block comprising:

a plurality of word lines;

a plurality of bit lines; and

a plurality of memory cells which are disposed at crossings of the word lines and the bit lines, each memory cell including first switching means and a capacitor which is connected to the bit line via the first switching means, the first switching means being turned on and off in accordance with a signal level supplied from the corresponding word line, and data being written to and read from the capacitor by a voltage signal supplied from the bit line,

wherein the semiconductor memory device includes;

a node comprising capacitance means having a predetermined capacitance;

second switching means for connecting the bit line to the node;

means for precharging the bit line;

means for precharging the capacitance means; and

control means for controlling the first switching means so as to connect electrically the memory cell which is coupled to the word line selected in a read operation to the corresponding bit line, and for controlling the bit line which is selected in the read operation to the node comprising the precharged capacitance means, whereby changing the electric potential of the selected bit line so as to applying a predetermined voltage signal to the capacitor of the selected memory cell which is coupled to the selected word line and the selected bit line, whereby reading a data signal corresponding the data stored in the capacitor of the selected memory cell onto the selected bit line and the node, wherein

the plurality of memory cells are arranged in a matrix,

the capacitor in each memory cell includes a pair of electrodes and a ferroelectric film provided therebetween, and stores the data in a nonvolatile manner, one of the electrodes being connected to the corresponding bit line via the first switching means,

the means for precharging the bit line precharges the plurality of bit lines to a first potential level which is the same as a potential level of the other electrode of the capacitor,

the means for precharging the capacitance means precharges the capacitance means to a second potential level which is different from the first potential level, and

the control means controls the first and second switching means so as to change the potential level of the one electrode of the capacitor of the selected memory cell to a third potential level between the first and second potential levels, whereby reading a data signal corresponding to the data stored in the ferroelectric film of the capacitor onto the selected bit line and the node.

5. A semiconductor memory device according to claim 4, wherein the means for precharging the capacitance means sets the second potential level so that a difference between the first and third potential levels is greater than a polarization inversion voltage of the ferroelectric film of the capacitor, the third potential level being obtained by charge-sharing between the one electrode of the capacitor of the selected memory cell, the selected bit line, and the capacitance means.

6. A semiconductor memory device including at least one memory block comprising:

a plurality of word lines;

a plurality of bit lines; and

a plurality of memory cells which are disposed at crossings of the word lines and the bit lines, each memory cell including first switching means and a capacitor which is connected to the bit line via the first switching means, the first switching means being turned on and off in accordance with a signal level supplied from the corresponding word line, and data being written in and read from the capacitor by a voltage signal supplied from the bit line,

wherein the memory block is divided into a plurality of sub-matrices each including a predetermined number of the bit lines,

and wherein the semiconductor memory device includes;

a first node provided for at least one sub-matrix of the at least one memory block, comprising first capacitance means having a first predetermined capacitance;

second switching means for selectively connecting the predetermined number of the bit lines included in each sub-matrix to the corresponding the first node;

a second node provided for the whole of the at least one memory block, comprising second capacitance means having a second predetermined capacitance;

third switching means for selectively connecting the first node to the second node;

means for precharging the plurality of bit lines;

first precharge means for precharging the first capacitance means;

second precharge means for precharging the second capacitance means; and

control means for controlling the first switching means so as to connect electrically the memory cell which is coupled to the word line selected in a read operation to the corresponding bit line, and for controlling the second switching means so as to connect electrically the bit line which is selected in the read operation to the first node comprising the precharged first capacitance means,

whereby changing the electric potential of the selected bit line so as to apply a predetermined voltage signal to the capacitor of a selected memory cell which is coupled to the selected word line and the selected bit line,

whereby reading a data signal corresponding the data stored in the capacitor of the selected memory cell onto the selected bit line and the first node, and

for controlling the third switching means so as to transfer the data signal which is read on the first node onto the second node.

7. A method for driving a semiconductor memory device including:

at least one memory block comprising;

a plurality of word lines;

a plurality of bit lines; and

a plurality of memory cells which are disposed at crossings of the word lines and the bit lines, each memory cell including first switching means and a capacitor which is connected to the bit line via the first switching means, the first switching means being turned on and off in accordance with a signal level supplied from the corresponding word line, and data being written in and read from the capacitor by a voltage signal supplied from the bit line;

a node comprising capacitance means having a predetermined capacitance; and

second switching means for connecting the bit line to the node,

the method including the steps of;

precharging the plurality of bit line to a first potential level;

precharging the capacitance means to a second potential level which is different from the first potential level;

turning on the first switching means coupled to the word line which is selected in a read operation whereby electrically connecting the capacitor of the corresponding memory cell to the corresponding bit line;

turning on the second switching means whereby electrically connecting the bit line which is selected in the read operation to the node comprising the precharged capacitance means;

changing the electric potential of the selected bit line whereby applying a predetermined voltage signal to the capacitor of the selected memory cell which is coupled to the selected word line and the selected bit line, as a result of turning on the first and second switching means; and

reading a data signal corresponding the data stored in the capacitor of the selected memory cell onto the selected bit line and the node.

8. A method for driving a semiconductor memory device according to claim 7, wherein the node comprising the capacitance means is provided for each of the plurality of bit lines,

and wherein in the step of turning on the second switching means, the bit line which is selected from the plurality of bit lines is connected to the corresponding node.

9. A method for driving a semiconductor memory device according to claim 7, wherein the node comprising the capacitance means is provided commonly for the plurality of bit lines,

and wherein in the step of turning on the second switching means, the bit line which is selected from the plurality of bit lines is connected to the node.

10. A method for driving a semiconductor memory device according to claim 7, wherein

the plurality of memory cells are arranged in a matrix,

the capacitor in each memory cell includes a pair of electrodes and a ferroelectric film provided therebetween, and stores the data in a nonvolatile manner, one of the electrodes being connected to the corresponding bit line via the first switching means, and

the node comprising the capacitance means is a common data line for carrying the data signal,

and wherein

in the step of precharging the bit line, the first potential level is the same as a potential level of the other electrode of the capacitor,

in the step of changing the electric potential of the selected bit line, the potential level of the one electrode of the capacitor of the selected memory cell is changed to a third potential level between the first and second potential levels, and

in the step of reading the data signal, the data signal corresponding to the data stored in the ferroelectric film of the capacitor is read onto the selected bit line and the common data line.

11. A method for driving a semiconductor memory device according to claim 10, comprising a step of allowing the common data line and the precharged bit lines to be in a floating state, prior to the read operation.

12. A method for driving a semiconductor memory device according to claim 10, wherein in the step of precharging the bit lines, all of the bit lines included in the memory block are precharged at the same time.

13. A method for driving a semiconductor memory device according to claim 10, wherein the step of turning on the second switching means is performed based on the column-address.

14. A method for driving a semiconductor memory device according to claim 10, wherein in the step of precharging the common data line, the second potential level is set so that a difference between the first and third potential levels is greater than a polarization inversion voltage of the ferroelectric film of the capacitor, the third potential level being obtained by charge-sharing between the one electrode of the capacitor of the selected memory cell, the selected bit line, and the common data line.

15. A method for driving a semiconductor memory device according to claim 10, further comprising a step of amplifying a signal level of the data which is read onto the common data line.

16. A method for driving a semiconductor memory device according to claim 15, further comprising the steps of

supplying a write signal corresponding to the read data to the common data line at the same time as or after performing the step of amplifying the signal level, a high level of the write signal for a data "1" being a fourth potential level, and

storing electric charge corresponding to the write signal in the capacitor of the selected memory cell.

17. A method for driving a semiconductor memory device according to claim 10, wherein in the step of turning on the first switching means, a signal of a predetermined potential level is applied to the first switching means via the selected word line, the predetermined potential level being higher than a fourth potential level by at least a threshold voltage of the first switching means, the fourth potential level being a high level of the write signal for a data "1".

18. A method for driving a semiconductor memory device according to claim 10, wherein in the step of turning on the second switching means, a signal of a predetermined potential level is applied to the second switching means via the selected bit line, the predetermined potential level being higher than a fourth potential level by at least a threshold voltage of the second switching means, the fourth potential level being a high level of the write signal for a data "1".

19. A method for driving a semiconductor memory device according to claim 16, wherein the fourth potential level is set at a source supply voltage level, and the first potential level is set at a half of the source supply voltage level.

20. A method for driving a semiconductor memory device according to claim 16, wherein the fourth potential level is set higher than a source supply voltage level, and the first potential level is set at a half of the fourth potential level.

21. A method for driving a semiconductor memory device including:

at least one memory block comprising;

a plurality of word lines;

a plurality of bit lines; and

a plurality of memory cells which are disposed at crossings of the word lines and the bit lines, each memory cell including first switching means and a capacitor which is connected to the bit line via the first switching means, the first switching means being turned on and off in accordance with a signal level supplied from the corresponding word line, and data being written to and read from the capacitor by a voltage signal supplied from the bit line,

the memory block being divided into a plurality of sub-matrices each including a predetermined number of the bit lines;

a first node provided for at least one sub-matrix of the at least one memory block, comprising first capacitance means having a first predetermined capacitance;

second switching means for selectively connecting the predetermined number of the bit lines included in each sub-matrix to the corresponding the first node;

a second node provided for the whole of the at least one memory block, comprising second capacitance means having a second predetermined capacitance; and

third switching means for selectively connecting the first node to the second node,

the method including the steps of;

precharging the bit lines to a first potential level;

precharging the first capacitance means to a second potential level which is different from the first potential level;

precharging the second capacitance means to a predetermined potential level;

turning on the first switching means connected to the word line which is selected in a read operation, whereby electrically connecting the capacitor of the corresponding memory cell to the corresponding bit line;

turning on the second switching means whereby electrically connecting the selected bit line to the first node comprising the precharged first capacitance means;

changing the electric potential of the selected bit line whereby applying a predetermined voltage signal to the capacitor of the selected memory cell which is coupled to the selected word line and the selected bit line, as a result of turning on the first and second switching means;

reading a data signal corresponding the data stored in the capacitor of the selected memory cell onto the selected bit line and the first node; and

turning on the third switching means whereby transferring the data which is read onto the first node to the second node line.