High speed serial data pin for automatic test equipment

• US 5,689,515 A
• Filed: 04/26/1996
• Issued: 11/18/1997
• Est. Priority Date: 04/26/1996
• Status: Expired due to Term

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Panis, Michael C.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/638,026
• Time in Patent Office: 571 Days
• Field of Search: 371/22.1, 371/25.1, 371/27, 371/61, 307/234, 307/303, 307/269, 395/550, 395/183.06, 395/421.08, 375/224, 375/225, 324/765, 324/73.1
• US Class Current: 714/724
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

A tester that produces digital timing signals having fast data rates including multiple groups of timing generators, multiple "exclusive-or" gates, and an "or" gate. Each group of timing generators is connected to an exclusive-or gate, and the output of each exclusive-or gate is coupled to the or gate. The digital timing signals are encoded such that the timing generators in each group may assert timing pulses only during specified cycles within a series of clock cycles. Each combination of timing generators within a group either asserting their respective encoded timing signals, or not asserting any timing signals during the series of clock cycles, generates a unique serial data stream. The serial data streams generated by the groups of timing generators are then combined to produce a new digital timing signal having a data rate that is faster than the data rate of the encoded digital timing signals.

Claims

1. A method of operating a tester to increase the data rate of digital timing signals produced by the tester, comprising:

(a) generating a plurality of groups of digital timing signals, each group of digital timing signals being generated during a different one of a plurality of non-overlapping time intervals;

(b) combining each group of digital timing signals generated in step (a) to produce a plurality of serial data streams, wherein each group of digital timing signals is combined in accordance with the Boolean logical "exclusive-or" operation; and

(c) combining the plurality of serial data streams produced in step (b) to produce a new digital timing signal, wherein the serial data streams are combined in accordance with the Boolean logical "or" operation, whereby the data rate of the new digital timing signal is faster than the data rate of each digital timing signal generated in step (a).

2. The method of claim 1,

wherein a plurality of clock cycles occurs during each non-overlapping time interval, and

wherein each digital timing signal generated in step (a) can be asserted only during specified clock cycles.

3. The method of claim 2,

wherein the same number of clock cycles occur during each time interval.

4. The method of claim 2,

wherein each digital timing signal is asserted for at least a minimum pulse width.

5. The method of claim 1,

wherein said generating in step (a) comprises

(a1) generating a first group of four digital timing signals during a first time interval, and

(a2) generating a second group of four digital timing signals during a second time interval.

6. The method of claim 5,

wherein four cycles of a clock occur during both the first time interval and the second time interval,

wherein said generating in step (a1) includes

(i) optionally generating a first timing signal, said first timing signal comprising a pulse asserted during cycles one and two of the clock,

(ii) optionally generating a second timing signal, said second timing signal comprising a pulse asserted during cycles three and four of the clock,

(iii) optionally generating a third timing signal, said third timing signal comprising a pulse asserted during cycles one, two and three of the clock, and

(iv) optionally generating a fourth timing signal, said fourth timing signal comprising a pulse asserted during cycles two, three, and four of the clock, and

wherein said generating in step (a2) includes

(i) optionally generating a fifth timing signal, said fifth timing signal comprising a pulse asserted during cycles five and six of the clock,

(ii) optionally generating a sixth timing signal, said sixth timing signal comprising a pulse asserted during cycles seven and eight of the clock,

(iii) optionally generating a seventh timing signal, said seventh timing signal comprising a pulse asserted during cycles five, six, and seven of the clock, and

(iv) optionally generating an eighth timing signal, said eighth timing signal comprising a pulse asserted during cycles six, seven, and eight of the clock.

7. The method of claim 6,

wherein each timing signal has a minimum pulse width equal to two cycles of the clock, and

wherein each timing signal has a minimum refire time equal to eight cycles of the clock.

8. The method of claim 1,

wherein each time interval is periodic.

9. The method of claim 8,

wherein each time interval has a period equal to a minimum refire time.

10. The method of claim 1,

wherein each serial data stream produced in step (b) corresponds to a different combination of digital timing signals.

11. A tester, adapted to produce a digital timing signal having a fast data rate, comprising:

(a) means for generating a plurality of groups of digital timing signals, wherein each group of digital timing signals is generated during a different one of a plurality of non-overlapping time intervals; and

(b) combinatorial logic, coupled to the means for generating digital timing signals, comprising

(i) a plurality of "exclusive-or" gates, each group of digital timing signals being applied to one of said plurality of "exclusive-or" gates, thereby producing a plurality of serial data streams, and

(ii) an "or" gate, coupled to each "exclusive-or" gate, thereby combining the serial data streams to produce a new digital timing signal having a fast data rate.

12. The tester of claim 11,

wherein a plurality of clock cycles occurs during each non-overlapping time interval, and

wherein each digital timing signal can be asserted only during specified clock cycles.

13. The tester of claim 11,

wherein each serial data stream corresponds to a different combination of digital timing signals applied to one of the plurality of "exclusive-or" gates.