Apparatus for scannable D-flip-flop which scans test data independent of the system clock

• US 5,689,517 A
• Filed: 07/26/1996
• Issued: 11/18/1997
• Est. Priority Date: 04/28/1994
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Ruparel, Kamalesh
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/686,506
• Time in Patent Office: 480 Days
• Field of Search: 371/22.3, 371/22.5, 371/22.1, 307/409, 307/418, 365/154, 365/189.05
• US Class Current: 714/731
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318541 Scan latches or cell details

Abstract

The present invention discloses an apparatus for controlling and observing test data stored in scannable-D-flip-flops independent of a system clock, thereby making the scannable-D-flip-flops well suited for partial scanning Design-For-Test (DFT) techniques. Under the present invention, the scannable-D-flip-flop is comprised of two master latches and one slave latch such that the scannable-D-flip-flops may operate in a normal mode of operation or a scan/test mode of operation. During normal mode of operation, the first master latch operates together with the slave latch in response to the system clock. During the scan/test mode of operation, the second master latch operates together with the slave latch in response to a scan clock. Since the scanning of external test data is controlled by the scan clock, the conventional non-scannable D-flip-flops in the design, which are controlled by the system clock, maintain their previous states during a scanning operation. Also disclosed is a method for performance testing integrated circuits utilizing the scanning application of the scannable-D-flip-flops. This is accomplished by constructing a test circuit that spans the entire silicon die area. By using a special AC-TEST-MODE control signal, the scannable D-flip-flops are set to a "flow-through" mode to provide a direct path through the scannable flip-flops such that the test circuit forms an oscillator in which the frequency of the device can be measured.

Claims

1. A scannable D-flip-flop circuit for processing data bits, said scannable D-flip-flop circuit comprising:

(a) a first latch circuit coupled to a first input of said scannable D-flip-flop, said first latch circuit receives a first data input signal and a first clock signal and stores said first data input signal in response to said first clock signal during a normal mode of operation, said first latch having an output;

(b) a second latch circuit coupled to a second input of said scannable D-flip-flop, said second latch circuit receives a second data input signal and a second clock signal and stores said second data input signal in response to said second clock signal during a scan mode of operation, said second latch having an output;

(c) a third latch circuit having a data path and a feedback path wherein said data path is coupled to said output of said first latch circuit and said feedback path is coupled to said output of said second latch circuit, said third latch circuit receives said first data input signal and said first clock signal and stores said first data input signal in response to said first clock signal during said normal mode of operation, said third latch circuit receives said second data input signal and said second clock signal and stores said second data input signal in response to said second clock signal during said scan mode of operation, said third latch circuit is coupled to an output of said D-flip-flop.

2. The scannable D-flip-flop circuit of claim 1, wherein said first and third latch circuits operate respectively as master and slave latch circuits in response to said first clock signal, and said second and third latch circuits operate respectively as master and slave latch circuits in response to said second clock signal.

3. The scannable D-flip-flop circuit of claim 1, wherein said first latch circuit comprises a first inverter having an input coupled to said first input of said scannable D-flip-flop, said first inverter having an output coupled to an input of a first transmission gate, said first transmission gate having an output coupled to an input of a second inverter, said second inverter having an output coupled to an output of said first latch circuit, said second inverter having said output coupled to an input of a third inverter, said third inverter having an output coupled to an input of a third transmission gate, said third transmission gate having an output coupled to said output of said first transmission gate;

during a first clock subcycle when a first signal of said first clock is in a first state, said first data input signal of said first latch circuit passes through to said output of said first latch circuit but is prevented from passing through to said input of said third latch circuit, furthermore, said first data input signal of said first latch circuit is prevented from latching into said first latch circuit;

during a second clock subcycle when said first signal of said first clock is in a second state, said first data input signal of said first latch circuit latches into said first latch circuit and passes through to said input of said third latch circuit.

4. The scannable D-flip-flop circuit of claim 3, wherein said third latch circuit comprises said second transmission gate having an input coupled to said input of said third latch circuit, said second transmission gate having an output coupled to an input of a fourth inverter, said fourth inverter having an output coupled to an input of a fifth inverter and coupled to an input of a sixth inverter having an output coupled to an output of said third latch circuit which is coupled to the output of said scannable D-flip-flop, said fifth inverter having an output coupled to an input of a fourth transmission gate, said fourth transmission gate having an output coupled to an input of a fifth transmission gate, said fifth transmission gate having an output coupled to said input of said fourth inverter and said output of said second transmission gate;

during said second clock subcycle when said first signal of said first clock is in said second state, said first data input signal of said first latch circuit passes from said output of said first latch circuit to said input of third latch circuit and through to said output of said third latch circuit, furthermore, said first data input signal of said first latch circuit is prevented from latching into said third latch circuit;

during a third clock subcycle when said first signal of said first clock is in said first state, said first data input signal of said first latch circuit that passes to said input of said third latch circuit during said second clock subcycle latches into said third latch circuit.

5. The scannable D-flip-flop circuit of claim 4, wherein said first latch circuit is available to receive a new first data input signal during said third clock subcycle.

6. The scannable D-flip-flop circuit of claim 1, wherein said second latch comprises a seventh inverter having an input coupled to said second input of said scannable D-flip-flop, said seventh inverter having an output coupled to an input of a sixth transmission gate, said sixth transmission gate having an output coupled to an input of an eighth inverter, said eighth inverter having an output coupled to an output of said second latch circuit and to an input of a ninth inverter, said ninth inverter having an output coupled to an input of a eighth transmission gate, said eighth transmission gate having an output coupled to said output of said sixth transmission gate;

during a first clock subcycle when a second signal of said second clock is in a first state and a control signal for selecting between a normal mode and a test mode of a scan clock driver circuit selects said normal mode of said scan clock driver circuit, said second data input signal of said second latch circuit passes through to said output of said second latch circuit but is prevented from passing through to said input of said third latch circuit, furthermore, said second data input signal of said second latch circuit is prevented from latching into said second latch circuit;

during a second clock subcycle when said second signal of said second clock is in a second state and said normal mode of said scan clock driver circuit is selected, said second data input signal of said second latch circuit latches into said second latch circuit and passes through to said input of said third latch circuit.

7. The scannable D-flip-flop circuit of claim 6, wherein said third latch circuit comprises a seventh transmission gate having an input coupled to an input of said third latch circuit, said seventh transmission gate having an output coupled to an input of a fourth inverter, said fourth inverter having an output coupled to an input of a sixth inverter having an output coupled to an output of said third latch circuit which is coupled to said output of said scannable D-flip-flop, said output of said fourth inverter further coupled to an input of a fifth inverter, said fifth inverter having an output coupled to an input of a fourth transmssion gate, said fourth transmission gate having an output coupled to an input of a fifth transmission gate, said fifth transmission gate having an output coupled to said output of said seventh transmission gate;

wherein said seventh transmission gate, said fourth inverter and said sixth inverter form said data path of said third latch circuit and said fifth inverter, said fourth transmission gate and said fifth transmission gate form said feedback path of said third latch circuit;

during said second clock subcycle when said second signal of said second clock is in said second state, said second data input signal of said second latch circuit passes from said output of said second latch circuit to said input of said third latch circuit and through to said output of said third latch circuit, furthermore, said second data input signal of said second latch circuit is prevented from latching into said third latch circuit;

during a third clock subcycle when said second signal of said second clock is in said first state, said second data input signal of said second latch circuit that passes to said input of said third latch circuit during said second clock subcycle latches into said third latch circuit.

8. The scannable D-flip-flop circuit of claim 7, wherein said second latch circuit is available to receive a new second data input signal during said third clock subcycle.

9. The scannable D-flip-flop circuit of claim 1, wherein said first clock generates a first clock signal from a system clock and a clock driver circuit, said first clock operates independently from said second clock.

10. The scannable D-flip-flop circuit of claim 1, wherein said second clock generates a second clock signal from a scan clock and a scan clock driver circuit, said second clock operates independently from said first clock.

11. The scannable D-flip-flop of claim 10, wherein said scan clock driver circuit comprises a first inverter having an input coupled to said input of said scan clock driver circuit, said first inverter having an output coupled to said input of a second inverter and a first input of a first multiplexer and a first input of a second multiplexer, said second inverter having an output coupled to a second input of said first multiplexer and a second input of said second multiplexer, said first multiplexer having an output coupled to a first output of said scan clock driver circuit, said second multiplexer having an output coupled to a second output of said scan clock driver circuit;

said scan clock driver circuit further comprises a control signal wherein said control signal selects a normal mode of operation of said scannable D-flip-flop or a test mode of operation of said scannable D-flip-flop, said normal mode of operation of said scannable D-flip-flop enables said second and third latch circuits to operate respectively as master and slave latch circuits in response to said second clock signal, said test mode of operation of said scannable D-flip-flop enables said second and third latch circuits to provide a direct path from said input of said second latch circuit to said output of said third latch circuit to provide a performance testing function for a device which contains said scannable D-flip-flops.

12. The scannable D-flip-flop circuit of claim 1, wherein said second clock signal is an edge-triggered clock signal.