Integrated circuits formed in radiation sensitive material and method of forming same

• US 5,691,089 A
• Filed: 06/07/1995
• Issued: 11/25/1997
• Est. Priority Date: 03/25/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Smayling, Michael C.
• Primary Examiner(s): Huff, Mark F.
• Application Number:
  US08/479,380
• Time in Patent Office: 902 Days
• Field of Search: 257/40, 257/660, 430/5, 430/322, 430/325
• US Class Current: 430/5
• CPC Class Codes: G03F 7/094 Multilayer resist systems, e.g. planarising layers
• CPC Class Codes: H05K 1/16 incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• CPC Class Codes: H10K 10/29 Diodes comprising organic-inorganic heterojunctions
• CPC Class Codes: H10K 10/46 Field-effect transistors, e.g. organic thin-film transistors [OTFT] H10K10/43 takes precedence
• CPC Class Codes: H10K 10/462 Insulated gate field-effect transistors [IGFETs]
• CPC Class Codes: H10K 10/468 characterised by the gate dielectrics
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 71/18 using non-liquid printing techniques, e.g. thermal transfer printing from a donor sheet
• CPC Class Codes: H10K 71/20 Changing the shape of the active layer in the devices, e.g. patterning
• CPC Class Codes: H10K 71/30 Doping active layers, e.g. electron transporting layers
• CPC Class Codes: H10K 85/111 comprising aromatic, heteroaromatic, or aryl chains, e.g. polyaniline, polyphenylene or polyphenylene vinylene
• CPC Class Codes: Y10S 428/901 Printed circuit
• CPC Class Codes: Y10T 428/24942 including components having same physical characteristic in differing degree
• CPC Class Codes: Y10T 428/24975 No layer or component greater than 5 mils thick

Abstract

A transistor device 10 is disclosed herein. A doped layer 14 of a radiation sensitive material is formed over a substrate 12. The radiation sensitive material 14 may be polyimide, polybenzimidazole, a polymer, an organic dielectrics, a conductor or a semiconductor and the substrate 12 may be silicon, quartz, gallium arsenide, glass, ceramic, metal or polyimide. A neutral (undoped) layer 16 of radiation sensitive material is formed over the doped layer 14. First and second source/drain regions 18 and 20 are formed in the neutral layer 16 and extend to a top portion of the doped layer 14. A gate region 22 is formed in a top portion of the neutral layer 16 between the first source/drain region 18 and second source/drain region 20 such that a channel region 24 is formed in the doped layer 14 beneath the gate region 22.

Claims

1. A transistor device comprising:

a first polarity doped layer of radiation sensitive polyimide formed over a substrate;

a neutral layer of radiation sensitive polyimide formed over said first polarity doped layer of radiation sensitive polyimide;

a first source/drain region of a second polarity formed in said neutral layer and extending to a top portion of said first polarity doped layer;

a second source/drain region of said second polarity formed in said neutral layer and extending to a top portion of said first polarity doped layer; and

a gate region formed in a top portion of said neutral layer between said first source/drain region and second source/drain region such that a channel region is formed in said doped layer beneath said gate region and insulated therefrom;

wherein said first source/drain region, said second source/drain region and said gate region are formed by irradiation.

2. The device of claim 1 wherein said doped layer comprises a p-doped layer.

3. The device of claim 1 wherein said substrate is selected from the group consisting of silicon, quartz, gallium arsenide, glass, ceramic, metal germanium, barium strontium titanate, mercury cadmium telluride, lithium niobate, and polyimide.

4. The device of claim 1 wherein said doped layer is between 0.1 and 2.0 microns thick and said neutral layer is between 0.1 and 0.5 microns thick.

5. The device of claim 1 and further comprising a contact layer of neutral, radiation sensitive material formed over said neutral layer wherein conductive contacts are formed within said contact layer.

6. The device of claim 5 and further comprising at least one interconnect region formed within said contact layer to electrically couple a corresponding contact to an element.

7. The device of claim 5 and further comprising at least one interconnect region to electrically couple a corresponding contact to an element, said at least one interconnect region formed in an interconnect layer of radiation sensitive material formed over said contact layer.

8. The device of claim 1 and further comprising an interconnect region formed said first polarity doped layer.

9. The device of claim 1 wherein the radiation sensitive material comprises a polyimide material having a conductivity threshold and an ablation threshold and having been increased in conductivity by electromagnetic irradiation in a range between the conductivity threshold and the ablation threshold.

10. A complementary transistor structure comprising:

a first undoped layer of radiation sensitive polyimide formed over a substrate;

an n-doped well region formed in said first undoped layer;

a p-doped well region formed in said first undoped layer and spaced from said n-doped well region;

a second undoped layer of radiation sensitive polyimide formed over said first undoped layer of radiation sensitive material;

first and second p-doped source/drain regions formed by irradiation in said second undoped layer and extending into at least a top portion of said n-doped well region;

a first gate region formed by irradiation in a top portion of said second undoped layer between said first and second source/drain p-doped regions such that a first channel region is formed in said n-doped well region beneath said first gate region;

first and second n-doped source/drain regions formed by irradiation in said second undoped layer and extending into at least a top portion of said p-doped well region; and

a second gate region formed by irradiation in a top portion of said second undoped layer between said first and second n-doped source/drain regions such that a first channel region is formed in said p-doped well region beneath said second gate region.

11. The structure of claim 10 wherein said substrate is selected from the group consisting of silicon, quartz, gallium arsenide, glass, ceramic, metal, germanium, barium strontium titanate, mercury cadmium telluride, lithium niobate and polyimide.

12. The structure of claim 10 and further comprising a contact layer of radiation sensitive material formed over said second undoped layer wherein conductive contacts are formed within said contact layer.

13. The structure of claim 12 and further comprising at least one interconnect region to electrically couple a corresponding contact to an element, said at least one interconnect region formed in an interconnect layer of radiation sensitive material formed over said contact layer.

14. A transistor device comprising:

a first layer of radiation sensitive polybenzimidazole (PBI) material formed over a substrate;

a non-conductive layer of radiation sensitive PBI material formed over said first layer of radiation sensitive material;

a first conductive source/drain region formed by irradiation in said non-conductive layer and extending to a top portion of said first layer;

a second conductive source/drain regions formed by irradiation in said non-conductive layer and extending to a top portion of said first layer, said first source/drain region spaced from said second source/drain region; and

a gate region formed by irradiation in a top portion of said non-conductive layer between said first source/drain region and second source/drain region such that a first channel region is formed in said first layer beneath said gate region and insulated therefrom.

15. The device of claim 14 wherein said first layer comprise a doped layer.

16. The device of claim 15 wherein said first layer comprises a p-doped layer.

17. The device of claim 14 wherein said non-conductive layer is a doped layer.

18. A field effect transistor device comprising:

a source region formed by irradiation of a first polarity doped radiation sensitive polymer material, said radiation sensitive polymer selected from the group consisting of polyimide and polybenzimidazole;

a drain region formed by irradiation of said first polarity doped radiation sensitive polymer material;

a channel region disposed between said source region and said drain region, said channel comprising a polymer material; and

a conductive gate disposed over said channel region, said conductive gate region being formed by irradiation of a radiation sensitive polymer material;

whereby said conductive gate is operable to actuate a current between said source region and said drain region upon application of a specified voltage.

19. The transistor of claim 18 wherein said radiation material is disposed over a substrate.

20. The transistor of claim 19 wherein said substrate is selected from the group consisting of silicon, quartz, gallium arsenide, glass, ceramic, metal, germanium, barium strontium titanate, mercury cadmium telluride, lithium niobate, and polyimide.

21. The transistor of claim 18 wherein said first polarity doped radiation sensitive material comprises n-doped material.

22. The device of claim 18 wherein the radiation sensitive material comprises a polyimide material having a conductivity threshold and an ablation threshold and having been increased in conductivity by electromagnetic irradiation in a range between the conductivity threshold and the ablation threshold.