MOS device structure and integration method
First Claim
1. A method of making MOS devices with salicided gate and source and drain, comprising the steps ofa. forming a pattern of field oxide on a silicon substrate using LOCOS;
- b. thermally growing a gate oxide layer on the silicon substrate in the active area defined by the field oxide window;
c. depositing a layer of polysilicon over the substrate;
d. depositing a layer of photoresist over the polysilicon, exposing the photoresist through a gate definition mask, developing the photoresist;
e. anisotropically reactive-ion etching the polysilicon and the gate oxide to form the polysilicon gate and the gate oxide, followed by the removal of the photoresist;
f. covering the substrate with a layer of silicon nitride by chemical vapor deposition;
g. anisotropically reactive-ion etching the silicon nitride to the end point defined by the exposure of the silicon substrate, thus forming the gate'"'"'s first sidewall spacer of silicon nitride;
h. then conformally depositing a layer of amorphous silicon over the topography of the silicon substrate, and defining the pattern using an active region definition mask;
i. implanting nitrogen into the amorphous silicon layer whereby as a result, nitrogen piles up at the interface between the native oxide layer on the amorphous silicon layer and the amorphous silicon layer in the gate and the source and drain areas where the surface of the amorphous silicon layer is perpendicular to the nitrogen ion beam;
j. thermally oxidizing the amorphous silicon in the sidewall areas not implanted with nitrogen to form the gate'"'"'s second sidewall of silicon dioxide;
k. implanting dopant into the amorphous silicon layer;
l. converting the amorphous silicon into polysilicon layer by annealing;
m. annealing to drive some implanted dopant into the single silicon substrate in the source and drain area to form shallow junctions, as well as into the polysilicon gate;
n. depositing a layer of refractory metal on polysilicon layer, followed by a first rapid thermal annealing to form silicide of the refractory metal;
o. removing the unsilicided metal covering the areas of field oxide and gate sidewall oxide; and
p. a second rapid thermal annealing to improve the conductivity of the silicide.
1 Assignment
0 Petitions
Accused Products
Abstract
This invention describes a new method for forming self-aligned silicide for application in MOSFET, and a new structure of MOSFET device featuring elevated source and drain, with the objectives of reducing silicide penetration into the source and drain junctions, of eliminating junction spikes, of obtaining smoother interface between the silicide and the silicon substrate, and of reducing the chance of bridging of the silicides on the gate and on the source and drain. The new structure is made by depositing an amorphous layer of silicon on a silicon substrate already patterned with field oxide, gate oxide, polysilicon gate, and silicon nitride spacer on the gate sidewalls. Novel oxide sidewall spacers are then created by first implanting nitrogen into the horizontal surface of the amorphous silicon layer and subsequently thermally oxidizing the part of the amorphous silicon on the vertical sidewalls that is not exposed to nitrogen implantation. A dopant implantation followed by an annealing at 600° C. in nitrogen converts the deposited silicon layer into elevated source and drains. A refractory metal, such as titanium is then deposited over the substrate and, upon rapid thermal annealing, reacts with the elevated source and drain polysilicon to form silicide without consuming the substrate silicon, and without ill effect on the source/drain junctions in the single crystalline silicon. The chance of silicide bridging is greatly reduced due to the special geometry of the novel sidewall oxide spacers.
-
Citations
15 Claims
-
1. A method of making MOS devices with salicided gate and source and drain, comprising the steps of
a. forming a pattern of field oxide on a silicon substrate using LOCOS; -
b. thermally growing a gate oxide layer on the silicon substrate in the active area defined by the field oxide window; c. depositing a layer of polysilicon over the substrate; d. depositing a layer of photoresist over the polysilicon, exposing the photoresist through a gate definition mask, developing the photoresist; e. anisotropically reactive-ion etching the polysilicon and the gate oxide to form the polysilicon gate and the gate oxide, followed by the removal of the photoresist; f. covering the substrate with a layer of silicon nitride by chemical vapor deposition; g. anisotropically reactive-ion etching the silicon nitride to the end point defined by the exposure of the silicon substrate, thus forming the gate'"'"'s first sidewall spacer of silicon nitride; h. then conformally depositing a layer of amorphous silicon over the topography of the silicon substrate, and defining the pattern using an active region definition mask; i. implanting nitrogen into the amorphous silicon layer whereby as a result, nitrogen piles up at the interface between the native oxide layer on the amorphous silicon layer and the amorphous silicon layer in the gate and the source and drain areas where the surface of the amorphous silicon layer is perpendicular to the nitrogen ion beam; j. thermally oxidizing the amorphous silicon in the sidewall areas not implanted with nitrogen to form the gate'"'"'s second sidewall of silicon dioxide; k. implanting dopant into the amorphous silicon layer; l. converting the amorphous silicon into polysilicon layer by annealing; m. annealing to drive some implanted dopant into the single silicon substrate in the source and drain area to form shallow junctions, as well as into the polysilicon gate; n. depositing a layer of refractory metal on polysilicon layer, followed by a first rapid thermal annealing to form silicide of the refractory metal; o. removing the unsilicided metal covering the areas of field oxide and gate sidewall oxide; and p. a second rapid thermal annealing to improve the conductivity of the silicide. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
Specification
-
- Resources
-
Current AssigneeTaiwan Semiconductor Manufacturing Company Limited
-
Original AssigneeTaiwan Semiconductor Manufacturing Company Limited
-
InventorsHsu, Shun-Liang, Tsai, Chaochieh
-
Primary Examiner(s)Niebling, John
-
Assistant Examiner(s)Mulpuri, S.
-
Application NumberUS08/721,665Time in Patent Office424 DaysField of Search437/20, 437/24, 437/27, 437/29, 437/46, 437/405 W, 437/415 W, 437/101, 437/162, 437/109, 437/200, 437/933, 437/950, 437/959, 437/413US Class Current438/297CPC Class CodesH01L 21/76895 Local interconnects; Local ...H01L 29/41783 Raised source or drain elec...H01L 29/66575 where the source and drain ...Y10S 438/92 Controlling diffusion profi...Y10S 438/966 Selective oxidation of ion-...
