Method of depositing tungsten nitride using a source gas comprising silicon

• US 5,691,235 A
• Filed: 06/12/1996
• Issued: 11/25/1997
• Est. Priority Date: 11/30/1994
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Meikle, Scott, Doan, Trung
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): BILODEAU, THOMA
• Application Number:
  US08/667,907
• Time in Patent Office: 531 Days
• Field of Search: 437/190, 437/192, 437/193, 437/60, 437/919
• US Class Current: 438/680
• CPC Class Codes: C23C 16/34 Nitrides C23C16/303 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 28/60 Electrodes

Abstract

A method for depositing tungsten nitride uses a source gas mixture having a silicon based gas, such as silane for depositing the tungsten nitride to overlie a deposition substrate. A non-planar storage capacitor has a tungsten nitride capacitor electrode.

Claims

1. A method for forming a layer overlying a substrate, comprising the following steps:

providing the substrate in a chamber;

introducing a gas comprising nitride into the chamber;

introducing a gas comprising tungsten into the chamber;

introducing a gas comprising silicon into the chamber;

providing conditions sufficient to deposit tungsten nitride; and

depositing a layer of tungsten nitride comprising silicon to overly the substrate.

2. The method as specified in claim 1, wherein said step of providing further comprises maintaining a temperature of an interior wall of the chamber at a temperature greater than 25 degrees Celsius.

3. The method as specified in claim 1, wherein said step of providing further comprises maintaining a temperature of an interior wall of the chamber at a temperature which minimizes adduct formation.

4. The method as specified in claim 1, further comprising:

forming a via;

depositing a portion of said layer of tungsten nitride comprising silicon in at least a portion of the via.

5. The method as specified in claim 1, further comprising:

providing a via;

lining a wall of the via with at least a portion of said layer of tungsten nitride comprising silicon; and

substantially filling a remaining portion of the via with tungsten.

6. The method as specified in claim 1, further comprising forming said layer of tungsten nitride comprising silicon between a polysilicon layer and a tungsten layer.

7. The method as specified in claim 6, further comprising patterning and etching said polysilicon layer, said layer of tungsten nitride comprising silicon and said tungsten layer to form a gate electrode.

8. The method as specified in claim 1, further comprising adjusting a flow rate of said gas comprising silicon to be within a range of 0.1% to 25% of a total flow rate of remaining gases introduced into said chamber.

9. The method as specified in claim 1, further comprising:

creating a first capacitor electrode layer overlying the substrate;

creating a dielectric layer overlying said first capacitor electrode layer;

depositing said layer of tungsten nitride comprising silicon to overly said dielectric layer; and

creating a second capacitor electrode from said layer of tungsten nitride comprising silicon.

10. The method as specified in claim 1, further comprising:

creating a first capacitor electrode layer overlying the substrate;

creating a dielectric layer of tantalum oxide overlying said first capacitor electrode layer;

depositing said layer of tungsten nitride comprising silicon to overly said dielectric layer; and

creating a second capacitor electrode from said layer of tungsten nitride comprising silicon.

11. A method for forming a layer overlying a substrate, comprising the following steps:

providing the substrate in a chamber;

introducing a gas comprising nitride into the chamber;

introducing a gas comprising tungsten into the chamber;

introducing a gas comprising silane into the chamber;

providing conditions sufficient to deposit tungsten nitride; and

depositing a layer of tungsten nitride comprising silicon to overly the substrate.

12. A method for forming a capacitor electrode, comprising the following steps:

providing a substrate in a chamber;

introducing a gas comprising nitride into the chamber;

introducing a gas comprising tungsten into the chamber;

introducing a gas comprising silicon into the chamber;

providing conditions sufficient to deposit tungsten nitride;

depositing a layer of tungsten nitride comprising silicon to overly the substrate;

patterning said layer of tungsten nitride comprising silicon to define the electrode; and

removing a portion of said layer of tungsten nitride comprising silicon, a remaining portion of said layer of tungsten nitride comprising silicon forming at least a portion of the capacitor electrode.

13. A method for forming a gate electrode, comprising the following steps:

providing a substrate in a chamber;

introducing a gas comprising nitride into the chamber;

introducing a gas comprising tungsten into the chamber;

introducing a gas comprising silicon into the chamber;

providing conditions sufficient to deposit tungsten nitride;

depositing a layer of tungsten nitride comprising silicon to overly the substrate;

patterning said layer of tungsten nitride comprising silicon to define the gate electrode; and

removing a portion of said layer of tungsten nitride comprising silicon, a remaining portion of said layer of tungsten nitride comprising silicon forming at least a portion of the gate electrode.

14. The method as specified in claim 13, further comprising:

forming a layer of silicon to overlie said substrate prior to said step of depositing said layer of tungsten nitride comprising silicon;

forming a layer of tungsten to overlie said layer of tungsten nitride comprising silicon; and

removing portions of said layer of tungsten and portions of said layer of silicon according to a pattern defined during said step of patterning, remaining portions of said layer of tungsten and said layer of silicon forming further portions of the gate electrode.